Chemical Mechanical Planarization: Advanced Material and Consumable Challenges

Abstract

The unprecedented and continuing increase in the computational power and functionality of microelectronic devices, extending beyond more-than-Moore, are driven by the ever shrinking dimensions of logic and memory circuits, now numbering over a billion and half, all packed into an area of ∼15 cm2. As the costs of these devices drop, they have become ubiquitous across the world, from high performance computing to smart phones to driverless cars to children’s toys. The most common substrate for these devices continues to be Si and the process sequence used to fabricate these devices is frequently divided into front-end-of-the-line (FEOL) and back-end-of-the-line (BEOL) processes, each with its own peculiar technological and manufacturing yield challenges. Once all the active circuit elements are fabricated in the Si substrate using FEOL processes, they need to be interconnected and also connected to an external power source to become functional. While new materials continue to be incorporated at various levels into the processing sequence, copper remains the metal of choice for the interconnect wiring which is created using BEOL processes. The Cu wiring itself is electrically insulated by a low-k dielectric and protected by a diffusion barrier layer that can also act as an adhesion promoter and, depending on its electrical conductivity, enable direct electroplating of Cu. The characteristics of the low-k dielectric and the barrier layer have an immense influence on the manufacturing process sequence as well as the performance and long term reliability of the devices. Significant advances continue to be made in identifying newer sets of materials to fill these roles, especially for the narrower Cu lines where the space for the liner is limited, along with the associated processing steps. While advances in lithographic techniques facilitated the feature size reduction that has already reached 14 nm in high volume commercial production and seemingly headed lower, the same advances in lithography also demand ever more stringent surface planarity requirements, both locally across the chip and more globally across the entire wafer. Chemical mechanical planarization (CMP) is the only technique that has so far been capable of achieving these demanding requirements at the large volume manufacturing level in spite of it being a counter intuitive process that is prone to non-uniform material removal, defects and contamination caused by pad debris, by the billions of abrasive particles contacting the wafer surface and by the host of reactive and nonreactive chemicals used in the planarization process. Mitigating such yield-diminishing factors is one of the major challenges driving the advances in CMP technology and led to improvements in the polisher components like wafer carrier, slurry delivery system, retainer ring, backing film, etc., as well as all the other consumables including polishing pads, conditioners, and polishing slurries. Given the heterogeneity and pattern density and feature size variations of the films being planarized on the wafer surface, process