Necessity of Cleaning and its Application in Future Memory Devices

Abstract

Concerning the processes of the semiconductor industry, device integration is increasing and cell structure is becoming more complicated, which brings many new kinds of challenges. The basic requirements for a future integration device are minimum feature size reduction with device integration and high-speed operation with sufficient cell capacitance. Many kinds of conventional films including electrode and dielectric materials should be altered to meet device requirements. Moreover, as the allowance level for contaminants on substrate surfaces becomes more stringent, the importance of removing them becomes even greater. Because of this, the semiconductor process for high quality device fabrication will never be realized without perfect cleaning on all surfaces. It is reported that the conventional cleaning solutions such as a NH4OH/H2O2/H2O (SC-1) solution (1:4:20, 80 °C), H2SO4/H2O2 (SPM) solution (4:1, 90 to 120°C), and HCl/H2O2/H2O (HPM) solution (1:1:6, 80 to 90°C) are not compatible with metal film exposed surfaces with very tiny patterns, due to the fast etching rate of metal films [1] . In 1995, at the base of the mechanism of the removal of the adhered contaminants such as metallic impurities, particles and organics, T. Ohmi proposed a total room temperature wet cleaning process (so called “UCT cleaning”) [2]. As a result of the continuous research on developed cleaning, the five steps process was revised to a four step room temperature wet cleaning for real device cleaning. The cleaning consists of 1) CO2 added O3-UPW cleaning for removing organic and metallic impurities, 2) NH3 added H2-UPW+MS cleaning for removing of particles, 3) HF/H2O2(FPM) cleaning for removing metallic impurities, and 4) H2-UPW+MS rinse for the removal of chemical residues, prevention of particle re-adhesion, suppression of native oxide growth, and enhancement of H-termination.