Recrystallized Polycrystalline Silicon Research Articles

Performance Investigation of Single Grain Boundary Junctionless Field Effect Transistor

In this paper, we report a single grain boundary (GB) junctionless thin film transistor (JLFET) on recrystallized polycrystalline silicon (poly-Si JLFET). Using 2-D simulations, the electrical performance of the poly-Si JLFET is evaluated for different single GB locations in the channel. Without the need for creating the source and the drain regions by implantation, we demonstrate the prospect of achieving thin-film poly-Si JLFETs whose performance is reasonable for silicon film thicknesses less than 10 nm.

Visualization and identification of nanoparticles in si subjected to the successive implantation of 64Zn+ and 16O+ ions

Nanoparticles are visualized and identified in a near-surface Si layer subjected to the successive implantation of 64Zn+ and 16O+ ions. Scanning transmission electron microscopy coupled with energy-dispersive spectroscopy and X-ray photoelectron spectroscopy are used. An amorphized region 150 nm thick and a disturbed layer 50 nm thick in the near-surface layer of the substrate are revealed after implantation. Zinc oxide (ZnO) nanoparticles with an average size of 8.7 nm are found in the recrystallized polycrystalline silicon layer after annealing in a neutral-inert atmosphere at a temperature of 600–800°C.

Single Grain Boundary Dopingless PNPN Tunnel FET on Recrystallized Polysilicon: Proposal and Theoretical Analysis

A single grain boundary dopingless PNPN tunnel field effect transistor (TFET) on recrystallized polycrystalline silicon is studied by varying the position of the grain boundary in the channel. The performance of the proposed device is assessed using 2-D simulations. We establish the prospect of realizing low-cost thin-film recrystallized polycrystalline tunnel FETs with: 1) low OFF-state current and low sub-threshold swing (SS) and 2) an ON-state current similar to that of a comparable single grain boundary poly-silicon thin film transistor (TFT). Our results indicate that the proposed single grain boundary dopingless PNPN TFET could be an ideal substitute for the conventional TFTs making it appropriate for low power display applications as well as the driver circuits.

Single Grain Boundary Tunnel Field Effect Transistors on Recrystallized Polycrystalline Silicon: Proposal and Investigation

A single grain boundary tunnel field effect transistor (TFET) on recrystallized polycrystalline silicon is reported in this letter. By varying the position of the grain boundary (GB) in the channel, the performance of the proposed device is evaluated using calibrated 2-D simulations. Our results show the possibility of realizing low-cost thin-film recrystallized polycrystalline tunnel FETs with low OFF-state current and low subthreshold swing compared with the thin-film transistors. By introducing the source N + pocket doping, it is also shown that the proposed single GB PNPN TFET exhibits enhanced ON-state current, making it suitable for low power display applications, including the driver circuits.

Thin-Film Bipolar Transistors on Recrystallized Polycrystalline Silicon Without Impurity Doped Junctions: Proposal and Investigation

A lateral polysilicon Bipolar Charge Plasma Transistor (poly-Si BCPT) on undoped recrystallized polycrystalline silicon which is compatible with the thin-film field effect transistor (TFT) fabrication is reported in this paper. Using calibrated two-dimensional device simulation, the electrical performance of the poly-Si BCPT is evaluated in detail by considering the position of the single grain boundary. Our simulation results demonstrate that the poly-Si BCPT has the potential to realize low-cost thin-film polycrystalline silicon bipolar transistors with large current gain and cut-off frequency making it suitable for a number of applications including the driver circuits of the displays.

Electrical Enhancement of Solid Phase Crystallized Poly-Si Thin-Film Transistors with Fluorine Ion Implantation

Solid phase recrystallized polycrystalline silicon thin-film transistors (SPC poly-Si TFTs) with fluorine ion implantation were investigated in this study. Electrical characteristics and reliability of the proposed poly-Si TFTs were improved effectively, especially for field effect mobility and off current. The fluorine-ion-implanted poly-Si TFT can suppress the hot carrier multiplication near the drain side, leading to superior endurance to electrical stress compared with conventional poly-Si TFTs. It was found that fluorine ions will pile up at the poly-Si interface during thermal annealing, without the initial deposition of pad oxide. The proposed technology is manageable and compatible with conventional poly-Si TFT fabrication. As the ion dosages increase more than , however, the electrical characteristics of poly-Si TFTs were degraded due to the increase of trap state density caused by the fluorine segregation in the poly-Si film.

Temperature-dependent thermal conductivity of undoped polycrystalline silicon layers

Polycrystalline silicon is used in microelectronic and microelectromechanical devices for which thermal design is important. This work measures the in-plane thermal conductivities of free-standing undoped polycrystalline layers between 20 and 300 K. The layers have a thickness of 1 +m, and the measurements are performed using steady-state Joule heating and electrical-resistance thermometry in patterned aluminum microbridges. The layer thermal conductivities are found to depend strongly on the details of the deposition process through the grain size distribution, which is investigated using atomic force microscopy and transmission electron microscopy. The room-temperature thermal conductivity of as-grown polycrystalline silicon is found to be 13.8 W } m &1 }K &1 and that of amorphous recrystallized polycrystalline silicon is 22 W } m &1 }K &1 , which is almost an order of magnitude less than that of single-crystal silicon. The maximum thermal conductivities of both samples occur at higher temperatures than in pure single-crystalline silicon layers of the same thickness. The data are interpreted using the approximate solution to the Boltzmann transport equation in the relaxation time approximation together with Matthiessen’s rule. These measurements contribute to the understanding of the relative importance of phonon scattering on grain and layer boundaries in polysilicon films and provide data relevant for the design of micromachined structures.

The Two-Step Rapid Thermal Annealing Effect of the Prepatterned A-SI Films

ABSTRACTHydrogenated amorphous silicon (a-Si:H) films which were deposited by plasma enhanced chemical vapor deposition (PECVD) have been recrystallized by the two-step rapid thermal annealing (RTA) employing the halogen lamp. The a-Si:H films evolve hydrogen explosively during the high temperature crystallization step. In result, the recrystallized polycrystalline silicon (poly-Si) films have poor surface morphology. In order to avoid the hydrogen evolution, the films have undergone the dehydrogenation step prior to the crystallization step.Before the RTA process, the active area of thin film transistors (TFT's) was patterned. The prepatterning of the a-Si:H active islands may reduce the thermal damage to the glass substrate during the recrystallization. The computer generated simulation shows the heat propagation from the a-Si:H islands into the glass substrate. We have fabricated the poly-Si TFT's on silicon wafers. The maximum ON/OFF current ratio of the devices was over 10.

Mechanical sensors based on laser-recrystallized SOI structures

Application of microzone laser recrystallization in the technology of microelectronic mechanical sensors is considered. Recent results concerning theoretical and experimental studies of recrystallized polycrystalline silicon on insulator resistors, improvement of pressure-sensor performance and creation of microelectronic sensors of force and acceleration are reported. It is shown theoretically and proved experimentally that dopant impurity (boron) concentrations of 1 × 10 18 – 1 × 10 19 cm 1 are the most advisable to apply laser recrystallization for the improvement of poly-Si resistors and mechanical sensors based on them. At dopant levels of 1 × 10 18 – 5 × 10 18 cm 3 the gauge factor increases 1.5–1.7 times due to the laser recrystallization, whilst the temperature characteristics of poly-Si resistors (temperature coefficient of resistivity and temperature coefficient of the gauge factor) decrease. Advantages of the developed mechanical sensors are high-temperature operating range, possibility to select the temperature coefficients by the choice of doping concentrations in polysilicon layers and reproducibility of the sensor fabrication process.

High-voltage TFT fabricated in recrystallized polycrystalline silicon

High-voltage thin-film transistors (TFTs) fabricated using CW-Ar laser annealed polycrystalline silicon have an offset gate structure between the source and gate and between the gate and drain. The breakdown voltage, transconductance, and leakage current in various size TFTs are described. These TFTs exhibited n-channel enhancement characteristics with a low-threshold voltage, and a breakdown voltage above 100 V could be obtained at an offset gate length of 20 mu m. Active TFT circuits were fabricated with these high-voltage Si TFTs. These high-voltage TFT circuits can drive thin-film EL (electroluminescent display) at low signal voltage. >

Low temperature processes MOSFET's using laser recrystallized polycrystalline silicon films: Han-Sheing Lee Solid St. Electron.26, (11) 1123 (1983)

Low temperature processes MOSFET's using laser recrystallized polycrystalline silicon films: Han-Sheing Lee Solid St. Electron.26, (11) 1123 (1983)

Low temperature processed MOSFET's using laser recrystallized polycrystalline silicon films : Han-Sheng Lee. Solid-St. Electron.26 (11), 1123 (1983)

Low temperature processed MOSFET's using laser recrystallized polycrystalline silicon films : Han-Sheng Lee. Solid-St. Electron.26 (11), 1123 (1983)

Liqiuid Crystal Display Fabricated from Laser Recrystallized Silicon on Bulk Fused Silica

ABSTRACTThis paper discusses four aspects of fabrication of an active address liquid crystal array from laser recrystallized polycrystalline silicon: recrystallization, processing, device performance and array fabrication. The recrystallization process produces material which is imperfect by silicon wafer standards, but which contains few incoherent defects. The material was used to fabricate discrete n-channel MOS devices which had consistent off currents of 10−11 amps (0.4pA/μm of channel width) and on currents of 10−4 amps. Device threshold is controlled to + 200 mV and channel mobility is 500 to 600 cm2 /V-sec. The crossovers between Al/1% Si source and degenerately doped polycrystalline silicon gate lines were fabricated by use of high temperature reflowed, phosphorus doped chemical vapor deposited SiO2. Completed arrays had very few defects (no crossover defects and 0.3% bad devices).

SOI-CMOS devices on beam-recrystallized polysilicon

Control of the grain boundary direction in the recrystallized polycrystalline silicon (polysilicon) island is achieved by the direction of the laser scanning. By using this technique, the source-to-drain short in a short-channel MOSFET is almost eliminated, and MOSFETs with channel lengths of 2–3 μm level in both n-channel and p-channel mode are fabricated with a good uniformity and reproducibility. The low-field electron and hole mobilities are 580 cm 2/Vsec and 220 cm 2/Vsec, respectively. 19-stage CMOS ring oscillators with nominal channel lengths of 3μm are fabricated. The minimum propagation delay is 280 psec/stage at a supply voltage of 10 V, and the minimum power delay product is 0.13 pJ/stage.

Low temperature processed mosfet's using laser recrystallized polycrystalline silicon films

An n-channel MOS transistor was fabricated on a laser recrystallized polycrystalline silicon film at temperatures below 630°C. The gate oxide was sputter deposited at 200°C. Lasers were used for substrate recrystallization, implantation damage annealing and dopant drive-in. An electron field effect mobility higher than 100 cm 2/V · sec. was observed on the finished transistors. With 10 V applied to the gate of the transistors for 2 hr, less than a 20 mV shift in threshold voltage was observed.

Field effect in large grain polycrystalline silicon

Measurements have been carried out on transistors made in laser recrystallized polycrystalline silicon. In these devices, grain size is comparable to channel dimensions. A 2-D investigation of the band curvature near a grain boundary has made it possible to model transistor characteristics. Good agreement has been found between theory and experiments.

Direct observation of grain boundary effects in polycrystalline silicon thin-film transistors

We have applied charge collection scanning electron microscopy to the gate capacitor of n-channel thin-film transistors that were fabricated in laser recrystallized polycrystalline silicon. The action of grain boundaries as impediments to channel current flow and as fast diffusion paths for source and drain dopants is directly observed.

P-N junction and Schottky barrier diode fabrication in laser recrystallized polysilicon on SiO2

P-N junction and Schottky barrier diodes have been fabricated in laser recrystallized polycrystalline silicon on SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> . A repetitively Q-switched Nd <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3+</sup> :YAG laser was used to anneal polysilicon deposited by LPCVD on oxide thermally grown on

Schottky-Diodes in Laser Recrystallized Polysilicon

ABSTRACTSchottky-diodes on laser recrystallized polycrystalline silicon are studied and compared to diodes fabricated on conventional, fine grained poly-Si. A strong dependence of reverse current on grain size is found and can be quantitatively explained by carrier generation at grain boundaries. In order to reduce the series resistance of the diodes, various methods to create a n+n doping profile in the recrystallized layer are investigated.