Reconfigurable FFT Research Articles

A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access

A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access

Reconfigurable and Resource Efficient Implementation of a Parallel FFT Core in FPGA

Resource efficient implementation of a highly reconfigurable, parallel and pipelined FFT core that provides 1.2GS/s throughput rate with 24-bits wide input samples for the real-time spectrum analysis applications is developed and realized. Physical placement constraints are used to improve the timing performance of implemented design in FPGA. Some design techniques to reduce the memory complexities of design are also provided. Full implementation of the design is completed and implementation details are provided.

An Efficient FPGA Architecture for Reconfigurable FFT Processor Incorporating an Integration of an Improved CORDIC and Radix-2r Algorithm

In ultra-high sampling rates, FFT is widely used for acoustic emission signals. In this manuscript, the effectual architecture of hardware is presented based on the execution of FFT due to radix-2 frequency decimation algorithm (R2DIF) and channeled method that allows data to be effectively shared through storage by shift registers. An optimal rotation method/design uses the modified digital coordinate rotation computer algorithm (m-CORDIC) as well as Radix- 2r depending on coding scheme to replace complex multiplier as FFT. The m-CORDIC algorithm enhances computing confluence, while Radix-2r allows the logarithmic reduction of the adder steps. The suggested design does not need large blocks of memory used to maintain the factor as twiddle. Experimental outcomes displays the presented design performs the existing methods by achieving high accuracy and throughput. Compared to the CSD as well as DBNS, novel radix-2r encoding desires an average of 23.12% and 3.07% fewer additions, respectively. The expansion of CSD is canonical signed-digit.

A power-efficient variable-length prime factor MDC FFT architecture for high-speed wireless communication applications

In this paper, a variable-size power-efficient two-parallel prime factor MDC FFT architecture is proposed which uses a novel reconfigurable processing element pair (RPEP). The prior reconfigurable FFT approaches merely concentrate on FFT architectures with a wide range of FFT sizes. The processing elements/stages are connected to or disconnected from the architecture to vary the size of the FFT. As a result, the hardware is underutilized when the processing elements are disconnected (unused). In the proposed approach, power reduction and effective utilization of hardware are concentrated rather than increasing the number of FFT sizes. The proposed RPEP structure contains two two-parallel processing element which can be either connected in serial or parallel. If one of the processing elements in the RPEP must be disconnected to reduce the FFT size, then the two two-parallel processing elements in the RPEP are configured as a single four-parallel processing element. Due to parallel processing, the frequency of operation is reduced by half and dynamic power is also reduced significantly. The architecture is designed in UMC 65 nm technology and can be configured in seventeen sizes ranging from 8 to 2048-points. The design occupies 0.67 mm.sq and consumption 17.74 mW power when operated at 100 MHz.

Fast Performance Pipeline Re-Configurable FFT Processor Based on Radix-22 for Variable Length N

Fast Performance Pipeline Re-Configurable FFT Processor Based on Radix-22 for Variable Length N

Improving Energy Efficiency of OFDM Using Adaptive Precision Reconfigurable FFT

Being an essential issue in digital systems, especially battery-powered devices, energy efficiency has been the subject of intensive research. In this research, a multi-precision FFT module with dynamic run-time reconfigurability is proposed to trade off accuracy with the energy efficiency of OFDM in an SDR-based architecture. To support variable-size FFT, a reconfigurable memory-based architecture is investigated. It is revealed that the radix-4 FFT has the minimum computational complexity in this architecture. Regarding implementation constraints such as fixed-width memory, a noise model is exploited to statistically analyze the proposed architecture. The required FFT word-lengths for different criteria--namely BER, modulation scheme, FFT size, and SNR--are computed analytically and confirmed by simulations in AWGN and Rayleigh fading channels. At run-time, the most energy-efficient word-length is chosen and the FFT is reconfigured until the required application-specific BER is met. Evaluations show that the implementation area and the number of memory accesses are reduced. The results obtained from synthesizing basic operators of the proposed design on an FPGA show energy consumption experienced a saving of over 80 %.

VLSI Implementation of Reconfigurable FFT Processor Using Vedic Mathematics

Fast Fourier transform has been used in wide range of applications such as digital signal processing and wireless communications. In this we present a implementation of reconfigurable FFT processor using single path delay feedback architecture. To eliminate the use of read only memory’s (ROM’S). These are used to store the twiddle factors. To achieve the ROM-less FFT processor the proposed architecture applies the bit parallel multipliers and reconfigurable complex multipliers, thus consuming less power. The proposed architecture, Reconfigurable FFT processor based on Vedic mathematics is designed, simulated and implemented using VIRTEX-5 FPGA. Urdhva Triyakbhyam algorithm is an ancient Vedic mathematic sutra, which is used to achieve the high performance. This reconfigurable DIF-FFT is having the high speed and small area as compared with other conventional DIF-FFT

High Real-Time Design of Digital Pulse Compression Based on FPGA

Because of the poor real-time performance of in-place fast Fourier transforms, a reconfigurable radix-4 FFT processor is studied and designed, which is based on decimation-in-time and single floating-point computation. The proposed method adopts “pipeline and parallel” structure for accessing multiple memories to improve the FFT processing speed, and then it is applied to digital pulse compression. The experimental result shows that the proposed FFT based on radix-4 computation can implement digital pulse compression rapidly under no adding hardware resources. The proposed method can be also applied to other radix FFTs.

A Reconfigurable Radix-r FFT Hardware Structure Design

A reconfigurable radix-r FFT structure design is proposed, to reduce the memory and time consumption caused by zero-paddling in traditional radix-2/4 methods. The radix-r FFT computing flow is divided into three iterative steps: rotate factors computation; memory access schedule; butterfly coefficients matrix multiplication. The hardware structure is depicted, in which the memory accessing schedule is implemented by a finite state machine, the rotate factors and butterfly coefficients are calculated by the Taylor series expansion. The time consumption of the proposed structure is analyzed, and with the arbitrary data points, an optimized radix can be used to minimize the computing time. Compared with traditional methods, the proposed design has the advantage of generality, less time consumption and hardware costs.

Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example

This paper presents a design methodology for power and area minimization of flexible FFT processors. The methodology is based on the power-area tradeoff space obtained by adjusting algorithm, architecture, and circuit variables. Radix factorization is the main technique for achieving high energy efficiency with flexibility, followed by architecture parallelism and delay line circuits. The flexibility is provided by reconfigurable processing units that support radix-2/4/8/16 factorizations. As a proof of concept, a 128- to 2048-point FFT processor for 3GPP-LTE standard has been implemented in a 65-nm CMOS process. The processor designed for minimum power-area product is integrated in 1.25 × 1.1 mm2 and dissipates 4.05 mW at 0.45 V for the 20 MHz LTE bandwidth. The energy dissipation ranging from 2.5 to 103.7 nJ/FFT for 128 to 2048 points makes it the lowest energy flexible FFT.

Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems

This paper presents a novel scalable and runtime dynamically reconfigurable FFT architecture for different wireless standards. With only 8 butterfly units, a reconfigurable FFT architecture for three different FFT points is realized using mixed radix-22/23/24 FFT algorithm in a modified Single-path Delay Feedback (SDF) pipelined architecture. Via a proper data flow reconfiguration it can support 64, 128 and 256. It can even be extended up to 8192-point transforms and uses only 13 butterfly units to realize 8192 points. This paper describes the implementation method of 256 and 128 point FFT, which is reconfigured partially from 64 point FFT. The whole system is implemented on a Xilinx XC2VP30 FPGA device. The implementation design addresses area efficiency and flexibility allowing the insertion of the partial modules dynamically to realize various FFT sizes. To verify the efficacy of this dynamic partial reconfigurable FFT design method, a conventional multiplexer based reconfigurable architecture was designed and tested on the same platform. Tested FPGA results for the Dynamic Partial Reconfigurable (DPR) method show the configuration time improvement and good area efficiency as compared to the reconfigurable architecture using conventional multiplexer techniques.

FPGA based Reconfigurable 2D FFT System

This paper develops a system level architecture for implementing a cost-efficient, FPGA-based reconfigurable two dimensional (2D) FFT system. The adopted approach considers both the hardware cost (in terms of FPGA resource requirements), and performance (in terms of throughput). These two extremes are optimized based on using run time reconfiguration, double buffering technique, shared Dual Ported RAM (DPRAM) modules and the “hardware virtualization” to reuse the available processing components. The system employs two one Dimensional (1D) FFT processor each with sixteen reconfigurable parallel FFT cores. Each core represents a 16 complex point parallel FFT engine. Thus the architecture supports transform length of 256X256 complex points, as a demonstrator to the design idea, using fixed-point arithmetic and has been developed using radix-4 butterfly architecture. The simulation results that have been performed using VHDL modeling language and ModelSim software shows that the full design can be implemented using single FPGA platform requiring about 50,000 Slices. Keywords: 2D Fast Fourier Transform Radix-4. Run Time Reconfiguration

Reconfigurable Homogenous Multi-Core FFT Processor Architectures for Hybrid SISO/MIMO OFDM Wireless Communications

Multi-core processors have been attracting a great deal of attention. In the domain of signal processing for communications, the current trends toward rapidly evolving standards and formats, and toward algorithms adaptive to dynamic factors in the environment, require programmable solutions that possess both algorithm flexibility and low implementation complexity. Reconfigurable architectures have demonstrated better tradeoffs between algorithm flexibility, implementation complexity, and energy efficiency. This paper presents a reconfigurable homogeneous memory-based FFT processor (MBFFT) architecture integrated in a single chip to provide hybrid SISO/MIMO OFDM wireless communication systems. For example, a reconfigurable MBFFT processor with eight processing elements (PEs) can be configured for one DVB-T/H with N=8192 and two 802.11n with N=128. The reconfigurable processors can perfectly fit the applications of Software Defined Radio (SDR) which requires more hardware flexibility.

High level modeling and automated generation of heterogeneous SoC architectures with optimized custom reconfigurable cores and on-chip communication media

In this paper we propose a framework for modeling and automated generation of heterogeneous SoC architectures with emphasis on reconfigurable component integration and optimized communication media. In order to facilitate rapid development of SoC architectures, communication-centric platforms for data intensive applications, high level modeling of reconfigurable components for quick simulation and a tool for generation of complete SoC architectures is presented. Four different communication-centric platforms based on traditional bus, crossbar, hierarchical bus and novel hybrid communication media are proposed. These communication-centric platforms are proposed to cater for the different communication requirement of future SoC architectures. Multi-Standard telecommunication application is chosen as our target application domain and a case study of WiMAX is used as a real world example to demonstrate the effectiveness of our approach. A system consisting of an ARM processor, reconfigurable FFT and reconfigurable Viterbi decoder is considered with the option of system scalability for future upgrades. Behavior of system with different communication platforms is analyzed for its throughput and power characteristics with different reconfigurable scenarios to show the effectiveness of our approach.

Low-cost reconfigurable VLSI architecture for fast fourier transform

In this paper, a low-cost reconfigurable FFT processor employing novel dual-path pipelined sharedmemory architecture is presented. Based on this architecture, an elaborate memory configuration scheme is designed to make single-port SRAM available. Moreover, a mixed-radix butterfly unit is also designed, which makes the processor capable of multimode operation. Compared with previous ones, the proposed architecture can greatly reduce area. In addition, an optimized data scaling approach is proposed and the Signal-to-Quantization Noise Ratio (SQNR) of an 8Kpoint fixed-point FFT can achieve 52.7dB with the wordlength of 13bit. A test chip for DVB-T/H is implemented with the proposed architecture and fabricated in 0.18-μm single-poly six-metal CMOS process. The core area of this chip is 2.83mm2 with the power dissipation of 25.8mW at 20MHz.

FPGA implementation of a re-configurable fft for multi-standard systems in software radio context

This study is focused on the Field Programmable Gate Array (FPGA) implementation of a re-configurable Fast Fourier Transform (FFT) operator able to provide Fourier transforms both over complex infinite field X and Galois finite Field GF. This new re-configurable FFT exploits to a great advantage the possibility to share hardware resources when considering multi-standard scenarios for software radio systems. A re-configurable FFT of length N = 256 has been implemented on FPGA. It achieves a performance-to-cost ratio gain from 24% to 9.4% compared to the basic duplicated solution for which no re-configuration is considered. The proposed technology is strongly connected to further consumer handheld devices such as mobile phones intended to support several standards (digital television, mobile communications, wireless local area network etc) where FFT is involved.