Reconfigurable CMOS Research Articles

A 0.5-8GHz Reconfigurable CMOS RF Receiver Front-End for CR and DPA Applications

A 0.5-8GHz Reconfigurable CMOS RF Receiver Front-End for CR and DPA Applications

Current Re-Use Architecture and Pre-Distortion Technique Employing Re-Configurable Low Noise Amplifier for the Design of Nano-Electronic Sensors

This study presents the design of reconfigurable CMOS Low Noise Amplifier (LNA) topologies to achieve acceptable linearity, gain, and low noise for Nano-sensor applications. The frequency bands at 2.4 GHz, 5 GHz and 28 GHz are taken into consideration for employing the Pre-distortion and current reuse technique. Millimeter Wave (MMW) frequency bands include excellent impedance matching, good isolation between the ports, To improve the futuristic applications of RADAR sensors, low noise figures and significant gain are preferred. The designed re-configurable structure achieved At 2.4 GHz, the gain is modest with a low NF of 2.6 dB, less than 2 dB at 5 GHz, and more than 10 dB at 28 GHz frequencies. The Stability of the amplifier greater than 1 dB, The arrangement of the layout with a chip measuring 0.5×0.2 mm2 and a moderate power increase make it appropriate for nanosensor creation.

Low-cost high-speed rapidly reconfigurable integrated half-duplex optical transceiver front-end.

We present and demonstrate an integrated approach to make low-cost high-speed half-duplex optical transceiver with rapid reconfigurability. A single Distributed-Feedback (DFB) diode is employed as the unified E/O-O/E device, which is dynamically biased as laser or photodetector in transmitter or receiver mode. The bias for the DFB and the transmit/receive (T/R) signal path are provided by a custom-designed reconfigurable CMOS chip, which contains the biasing circuitry, a high-speed T/R switch and a burst-mode transimpedance amplifier (BM-TIA). The transceiver front-end operates up to 5 Gb/s for both transmitter (Tx) and receiver (Rx) mode experimentally, while its reconfiguration time is less than 131 ns. This integrated approach not only halves the transceiver optics to facilitate low cost, but also enables high-speed signal transmission as well as rapid reconfiguration, which will be critical for the fiber-to-everything paradigm shift in the near future.

A Reconfigurable CMOS Ising Machine With Three-Body Spin Interactions for Solving Boolean Satisfiability With Direct Mapping

A Reconfigurable CMOS Ising Machine With Three-Body Spin Interactions for Solving Boolean Satisfiability With Direct Mapping

A 2.2–3.6 GHz CMOS Reconfigurable Fourth-Order Bandpass Filter With Compact Size and High Selectivity Using Transformer-Type Resonators

A compact reconfigurable CMOS bandpass filter (BPF) with high selectivity is proposed using transformer-type resonators in this article. The transformer-type resonator is constructed by a transformer loaded with parallel varactors for frequency tuning, and two varactors are then added across primary wind and secondary wind for coupling tuning. With the transformer-type structure, one resonator is formed inside another resonator, thus fully utilizing the chip area and resulting in a miniaturized structure. Magnetic and electrical couplings are formed within the transformer-type resonator and facilitate the bandwidth (BW) tuning. The quality factor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> ) of each resonator is improved by cross-coupled negative resistance structure. Meanwhile, two pairs of transformer-type resonators are placed side-by-side and naturally form a quadruplet structure; as a result, two transmission zeros (TZs) are introduced at each side of the passband thus significantly improving the selectivity and stopband rejection of the BPF. The proposed tunable on-chip BPF is manufactured by a commercial 55 nm bulk CMOS technology with a core area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.48 \times 0.54$ </tex-math></inline-formula> mm2. The filter center frequency (CF) can be tuned from 2.2 to 3.6 GHz, while the 3 dB fractional BW (FBW) can be tuned from 14% to 33%. The shape factor of the proposed filter is 1.4–1.9.

A Compact, Reconfigurable CMOS RF Receiver for NavIC/GPS/Galileo/BeiDou

This article presents a fully integrated low-intermediate frequency (IF) receiver, Dhruva, for global navigation satellite system (GNSS). The compact receiver uniquely features a fully programmable IP with no external components and no change in the on- chip hardware for various GNSS signals (civilian and precise positioning). The receiver bandwidth is programmable from 2 to 24 MHz for signals around <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L1$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L2$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L5$ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S$ </tex-math></inline-formula> frequency bands from Navigation with Indian Constellation (NavIC), global positioning system (GPS), Galileo, and BeiDou. A single-to-differential wideband input-matched noise-canceling low-noise amplifier (LNA) is proposed to avoid the external balun and matching components. An on- chip fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> phase-locked loop (PLL) with a single voltage-controlled oscillator (VCO) generates the required local oscillator (LO) frequencies. A dc offset correction circuit is proposed in the variable gain amplifier (VGA) to avoid signal saturation. Fabricated in 65-nm CMOS technology, the receiver draws a current of 38.35 mA from a 1.2-V supply while providing a maximum gain of 101.72 dB with a programmable gain of 53.53 dB and a minimum noise figure (NF) of 3.8 dB. The receiver occupies an active die area of 1.96 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , including the I/O padring with ESD protection.

A Wideband Reconfigurable CMOS VGA Based on an Asymmetric Capacitor Technique with a Low Phase Variation

This paper presents a wideband digitally controlled variable gain amplifier (VGA) with a reconfigurable gain tuning range and gain step in a 65 nm CMOS process. A unique asymmetric capacitor-based reconfigurable technique is proposed to extend the gain tuning range and realize gain step reconfiguration. An active neutralization topology based on a stackless transistor is utilized to compensate for the additional phase shift introduced by the gain tuning. Moreover, a current-type digital-to-analog converter (DAC) is also integrated for easier precise gain control. With the asymmetric capacitor varying from 1000 fF to 200 fF with a step of 400 fF, the proposed VGA achieves a 12.2/9.2/6.1 dB gain tuning range with a 0.4/0.3/0.2 dB gain resolution, respectively. At the maximum gain tuning range mode, the measured minimum root-mean-square (RMS) phase error is 1.7° at 23.4 GHz. At the finest gain step control mode, the RMS phase error measured across 20–30 GHz is lower than 1.9°. The tested result also shows the proposed VGA achieves a peak gain of 13 dB with a 3 dB bandwidth of 21.4–29 GHz, and the output 1 dB compression point (OP1dB) is up to 8.6 dBm at 25 GHz.

A K/Ka-Band Switchless Reconfigurable 65 nm CMOS LNA Based on Suspended Substrate Coupled Line

This article presents a K/Ka (18-40) GHz dual-band switch-free reconfigurable 65nm CMOS Low-Noise Amplifier (LNA) realized by inter-stage and output-stage Suspended-Substrate Coupled-Lines (SSCL) for the first time to the author’s best knowledge. The amplified input signal from the broadband drive stage is divided into two parallel single band stages by the proposed inter-stage SSCL. Two split-band signals are amplified by the corresponding High-band (Ka) and Low-band (K) stages. The proposed output-stage SSCL combines the amplified two single-bands at the output. The proposed SSCL also provides the required network matching to the LNA. The single band of operation can be achieved by simply turning off the unused transistor band’s drain voltage. The proposed LNA achieves a maximum noise figure (NF) taken in dual-mode of 1 dB and 1.2 dB and a gain of 27 dB with 0.2 dB and 2 dB variation in the K-band and Ka-band, respectively. Statistical analysis and design of experiment (DoE) are applied to predict the percentage error tolerance and validate the contribution of the parameters towards gain, return loss, and noise figure. This LNA exhibits an input and output 1-dB compression point (IP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> & OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ), third-order input & output intercept point (IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> & OIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) of −17/−16 dBm, +7.1/6.4 dBm, 0 dBm and +25/+23 dBm over 18-24/25-40 GHz respectively. The fabricated LNA draws 21.4 mA from 1.2 V with a size of 0.61 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 0.92 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Fine-Grain Reconfigurable Logic Circuits for Adaptive and Secure Computing via Work-Function Engineered Schottky Barrier FinFETs

A comprehensive simulation study has been conducted to show fine-grain reconfigurability in CMOS circuits using work-function engineering (WFE) on Schottky Barrier (SB) FinFETs for sub-10nm gate length. The study has three subsections. First, two-transistor (2T) & 4T AOI (and-or-invert)/ OAI (or-and-invert) gates with select bits that allow multiple logic functions are introduced. Secondly, the use of WFE to create ultra-compact reconfigurable logic circuits of fundamental operations (0,1,OR, AND,NAND,NOR,XOR) are explored via novel 2T, 3T and 4T gates. These circuits include one or two select bits that are capable of commanding up to four functions with two inputs. To further illustrate the potential of WFE for reconfigurable logic, novel multi-stage circuits such as compact full-adders are also modelled via TCAD simulations. Power×delay product (PDP) figures and DC gain of the proposed gates are quantified and compared against the CMOS designs with similar functionality. Finally, we also design a novel compact one-bit arithmetic logic unit (ALU) which has seven exclusive logic operations (1, NAND, OR, XOR, NOR, Addition, Subtraction) with three select bits using only 26 SB-FinFETs, saving substantial amount of power and chip area. The trade-offs between the number of metal work-functions used in the designs, circuit complexity and simulated performance metrics are also provided. The comparative simulations between reconfigurable SB-FinFET based designs versus conventional p-n junction FinFET circuits show that WFE can lead to absolutely minimalist reconfigurable CMOS logic blocks using ×3 to ×10 less power and between ×2 and ×15 less area than static CMOS counterparts. Although they suffer greater delays (×2 to ×5), the overall PDP performance remains comparable to conventional CMOS.

Single-Chip CMOS Reconfigurable Dual-Band Tri-Mode High-Efficiency RF Amplifier Design

This brief presents a new design methodology of single-chip reconfigurable CMOS RF power amplifier (PA) supporting both dual-band and multi-power-mode operation. The proposed architecture utilizes a novel switched-capacitor based output network to facilitate differential signal combining and impedance transformation at two widely separated frequency bands. It can offer three distinct output power levels (saturation) to be selected for multi-power-mode applications. Besides, closed-form explicit equations are readily available for the evaluation of component values. For verification, a PA operating at 1.8/2.6 GHz (non-concurrent), with three distinct saturation power levels (21, 23, 26 dBm) and peak efficiency of about 30%, is designed and fabricated using 0.35 μm CMOS process.

A reconfigurable CMOS sensor for tracking, pre-shower and digital electromagnetic calorimetry

Recent advances in CMOS imaging sensor technology have led to designs able to withstand much higher radiation levels, up to those required at hadron colliders for all but the innermost layers. Also, with stitching, wafer scale devices have been fabricated on the same process as used for the prototypes described in this submission, for applications such as, for example, direct electron detection in transmission electron microscopy. A small sensor prototype has been designed and fabricated in the TowerJazz 180 nm CMOS imaging process. The prototype has a pixel matrix of 64x64 pixels with a pitch of 55 x 55μm and reads out using fast logic at 40 MHz. Each pixel contains four collection electrodes, trimming logic, pre-amplifier, shaper and discriminator with digital output. It can be reconfigured to function as either a binary short strip sensor, for particle tracking including as a pre-shower, or as a pad sensor, counting the number of pixels above threshold for digital calorimetry. As well as providing a seamless transition from outer tracking to EM calorimetry, for optimal use of particle flow algorithms, digital calorimetry also can give excellent energy resolution. This concept is proposed as a possible option for future digital calorimeters able to read-out at LHC collision rates with good radiation hardness and realisable in low cost commercial technologies for equipping large areas. Results on physics performance simulation in a FCC-hh context and the characterisation of the prototype sensor are presented. The summing logic is demonstrated and the analogue pixel performance is validated by illuminating a test pixel within the matrix with a laser of wavelength of 1064 nm. The absolute laser intensity is calibrated such that the injected charge is similar to that expected for a minimum ionising particle. The measured pre-amplifier and shaper signals are compared to Cadence simulations. Laser illuminations in the digital pixel area and the response measured using a threshold scan confirm successful digital functionality in strip and pad operation modes.

A Reconfigurable CMOS Inverter-based Stacked Power Amplifier with Antenna Impedance Mismatch Compensation for Low Power Short-Range Wireless Communications

A reconfigurable CMOS inverter-based stacked power amplifier (PA) is proposed to extend impedance coverage, while maintaining an output power exceeding the specific power level under the worst antenna impedance mismatch conditions. The adopted process technology supports multi-threshold metal-oxide-semiconductor field-effect transistor (MOSFET) devices, and therefore, the proposed PA employs high threshold voltage (Vth) MOSFETs to increase the output voltage swing, and the output power under a given load condition. The unit cell of the last PA stage relies on a cascode inverter that is implemented by adding cascode transistors to the traditional inverter amplifier. By stacking two identical cascode inverters, and enabling one or both of them through digital switch control, the proposed PA can control the maximum output voltage swing and change the optimum load Ropt, resulting in maximum output power with peak power added efficiency (PAE). The cascode transistors mitigate breakdown issues when the upper cascode inverter stage is driven by a supply voltage of 2 × VDD, and decrease the output impedance of the PA by changing its operation mode from the saturation region to the linear region. This variable output impedance characteristic is useful in extending the impedance coverage of the proposed PA. The reconfigurable PA supports three operation modes: cascode inverter configuration (CIC), double-stacked cascode inverter configuration (DSCIC) and double-stacked inverter configuration (DSIC). These show Ropt of around 100, 50 and 25 Ω, respectively. In the simulation results, the proposed PA operating under the three configurations showed a saturated output power (Psat) of +6.1 dBm and a peak PAE of 41.1% under a 100 Ω load impedance condition, a Psat of +4.5 dBm and a peak PAE of 44.3% under a 50 Ω load impedance condition, and a Psat of +5.2 dBm and a peak PAE of 37.1% under a 25 Ω load impedance condition, respectively. Compared to conventional inverter-based PAs, the proposed design significantly extends impedance coverage, while maintaining an output power exceeding the specific power level, without sacrificing power efficiency using only hardware reconfiguration.

Dual PN Source/Drain Reconfigurable FET for Fast and Low-Voltage Reprogrammable Logic

Schottky junction reconfigurable FETs suffer from limited output currents to drive the following stages, jeopardizing their viability for high-end applications. This drawback becomes dramatic at low voltages. In this work, an analogous novel low-bias reprogrammable device is presented. It features a dual PN doping at source and drain which improves the driving current density thanks to the presence of both electron and hole reservoirs within the same structure. 3D-TCAD results for this innovative device on advanced Silicon-on-Insulator technology are presented and compared with traditional reconfigurable FETs and CMOS structures.

A reconfigurable highly-linear CMOS transceiver core chip for X-band phased arrays

This paper presents a highly-linear transceiver core chip for X-band phased-array systems with two RX and one TX channels. Implemented in a standard 0.18-μm CMOS technology, the core chip provides 6-bit phase control (with rms error <2°) and 6-bit gain control (with rms error <0.6 dB) both within the 8.5–11.5 GHz frequency band. Improved accuracy is also available by digital calibration in narrowband applications. The receivers achieve a gain of 13.5 dB, an IIP3 of +10.3 dBm, and a noise figure of 8.2 dB, while drawing 170 mA per channel from the 3.3 V supply. The chip also provides an additional low-gain mode which further enhances IIP3 to +19.1 dBm and the input-referred P1dB to +11.4 dBm. The transmitter gain is about 17 dB with an output-referred P1dB of +12.4 dBm and 160 mA dc bias current. The power consumption of the chip is digitally adjustable to enable the power/performance trade-off necessary for use in different applications.

A Self-Regulated and Reconfigurable CMOS Physically Unclonable Function Featuring Zero-Overhead Stabilization

This article presents a reconfigurable physically unclonable function (PUF) design fabricated using 65-nm CMOS technology. A subthreshold-inverter-based static PUF cell achieves 0.3% native bit error rate (BER) at 0.062-fJ per bit core energy efficiency. A flexible, native transistor-based voltage regulation scheme achieves low-overhead supply regulation with 6-mV/V line sensitivity, making the PUF resistant against voltage variations. Additionally, the PUF cell is designed to be reconfigurable with no area overhead, which enables stabilization without redundancy on chip. Thanks to the highly stable and self-regulated PUF cell and the zero-overhead stabilization scheme, a 0.00182% native BER is obtained after reconfiguration. The proposed design shows 0.12%/10 {\deg}C and 0.057%/0.1-V bit error across the military-grade temperature range from -55 {\deg}C to 125 {\deg}C and supply voltage variation from 0.7 to 1.4 V. The total energy per bit is 15.3 fJ. Furthermore, the unstable bits can be detected by sweeping the body bias instead of temperature during enrollment, thereby significantly reducing the testing costs. Last but not least, the prototype exhibits almost ideal uniqueness and randomness, with a mean inter-die Hamming distance (HD) of 0.4998 and a 1020x inter-/intra-die HD separation. It also passes both NIST 800-22 and 800-90B randomness tests.

A 2.4 GHz CMOS Class-F Power Amplifier With Reconfigurable Load-Impedance Matching

A novel reconfigurable CMOS class-F power amplifier (PA) at 2.4 GHz is proposed in this paper. It is able to match the output load variations mainly due to the effect of hand and head on a mobile phone. The effect of load variation on power-added efficiency (PAE), output power, and distortion is compensated by reconfiguring the output network using an impedance tuner. The tuner controls the output matching at fundamental frequency without affecting the class-F harmonic tuning up to 3rd harmonic. To the best of our knowledge, this is the first design of a CMOS class-F PA addressed to compensate the effect of load variation. Measurement results for $50~\Omega $ load impedance show a maximum PAE of 26% and maximum output power of 19.2 dBm. The measured total harmonic distortion is 4.9%. Measurement results for load values other than $50~\Omega $ show that PAE increases from 6.5% (not-tuned PA) up to 19.9% (tuned PA) with the same output power (19.2 dBm). Tuning also reduces the adjacent-channel leakage ratio by 5 dB and the spectral regrowth of a Wi-Fi signal at the PA output. The size of the fabricated chip is 1.6 mm $\times1.6$ mm.

Design Considerations of Reconfigurable CMOS Mixers for Multi-Standard Communication Receiver Systems

This paper has been carried out the study of reconfigurable wide-band mixers that can do the frequency conversion and gain variation standards with low noise and high linearity used in multi-mode and multi-standard receivers. Over the last few years reconfigurability has become very popular in adopting technology to meet the wideband wireless communication specifications that is compatible with multi-standards like GPS (1.57 GHz), WLAN (2.4 GHz - 5.9 GHz), Bluetooth (2.402 – 2.483 GHz) and ZigBee (0.784 - 0.915 GHz) in low power consumption environment. The reconfigurability can be achieved between low and high band modes through power switching in RF frequency mixers. It can be achieved by flipping the input RF signal between gate and source terminal of input transistor and altering the trans-impedance stage output. With the concept of reconfigurable transistor pair with open and short circuit stubs, one can not only find the configurable gain with center frequencies 7.355, 8.65, 11.35 and 12.65 GHz but also with high power efficiency. Tow Thomas Bi-Quad Topology other than the traditional current commuting technique for the second order trans-impedance amplifier stage, works as a current mode filter over a tunable bandwidth. The active Gilbert mixers are used widely in most of communication system, due to its significance gain, perfect isolation, and linearity in response.

Design Considerations of Reconfigurable CMOS Mixers for Multi-Standard Communication Receiver Systems

This paper has been carried out the study of reconfigurable wide-band mixers that can do the frequency conversion and gain variation standards with low noise and high linearity used in multi-mode and multi-standard receivers. Over the last few years reconfigurability has become very popular in adopting technology to meet the wideband wireless communication specifications that is compatible with multi-standards like GPS (1.57 GHz), WLAN (2.4 GHz - 5.9 GHz), Bluetooth (2.402 – 2.483 GHz) and ZigBee (0.784 - 0.915 GHz) in low power consumption environment. The reconfigurability can be achieved between low and high band modes through power switching in RF frequency mixers. It can be achieved by flipping the input RF signal between gate and source terminal of input transistor and altering the trans-impedance stage output. With the concept of reconfigurable transistor pair with open and short circuit stubs, one can not only find the configurable gain with center frequencies 7.355, 8.65, 11.35 and 12.65 GHz but also with high power efficiency. Tow Thomas Bi-Quad Topology other than the traditional current commuting technique for the second order trans-impedance amplifier stage, works as a current mode filter over a tunable bandwidth. The active Gilbert mixers are used widely in most of communication system, due to its significance gain, perfect isolation, and linearity in response.

A Temperature-Compensated Single-Crystal Silicon-on-Insulator (SOI) MEMS Oscillator with a CMOS Amplifier Chip.

Self-sustained feedback oscillators referenced to MEMS/NEMS resonators have the potential for a wide range of applications in timing and sensing systems. In this paper, we describe a real-time temperature compensation approach to improving the long-term stability of such MEMS-referenced oscillators. This approach is implemented on a ~26.8 kHz self-sustained MEMS oscillator that integrates the fundamental in-plane mode resonance of a single-crystal silicon-on-insulator (SOI) resonator with a programmable and reconfigurable single-chip CMOS sustaining amplifier. Temperature compensation using a linear equation fit and look-up table (LUT) is used to obtain the near-zero closed-loop temperature coefficient of frequency (TCf) at around room temperature (~25 °C). When subject to small temperature fluctuations in an indoor environment, the temperature-compensated oscillator shows a >2-fold improvement in Allan deviation over the uncompensated counterpart on relatively long time scales (averaging time τ > 10,000 s), as well as overall enhanced stability throughout the averaging time range from τ = 1 to 20,000 s. The proposed temperature compensation algorithm has low computational complexity and memory requirement, making it suitable for implementation on energy-constrained platforms such as Internet of Things (IoT) sensor nodes.

Integrated Quasi-Circulator With RF Leakage Cancellation for Full-Duplex Wireless Transceivers

An integrated reconfigurable CMOS quasi-circulator operating at 2.4 GHz is presented. A passive structure delivers transmit power amplifier (PA) output signal to the differential low-noise amplifier (LNA) input as a common-mode signal and simultaneously delivers received signal as a differential-mode signal at the LNA input. The leakage of the PA output signal at the LNA input is reduced in two steps. First, the use of a reconfigurable impedance matching circuit, instead of a fixed 50- $\Omega $ resistance reduces the leakage by compensating the antenna impedance mismatch, and improves transmitter–receiver isolation. Second, a reconfigurable summing stage adds amplitude and phase adjusted PA output signal to LNA output to cancel the residual PA output leakage. Measurement results show that the receiver achieves a reduction of 90 dB for a single tone and more than 50 dB for a QPSK modulated 40-MHz bandwidth transmit signal. The receiver gain is more than 10 dB and the noise figure in the receiver path is 4.5 dB. The reconfigurable quasi-circulator along with the receiver LNA is designed and fabricated on a 130-nm CMOS technology. The cancellation circuitry occupies 0.27 mm2 and consumes 30-mW quiescent power, while the total active area of the chip is 1 mm2, and it consumes 65-mW power.