Abstract
This article presents a fully integrated low-intermediate frequency (IF) receiver, Dhruva, for global navigation satellite system (GNSS). The compact receiver uniquely features a fully programmable IP with no external components and no change in the on- chip hardware for various GNSS signals (civilian and precise positioning). The receiver bandwidth is programmable from 2 to 24 MHz for signals around <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L1$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L2$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L5$ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S$ </tex-math></inline-formula> frequency bands from Navigation with Indian Constellation (NavIC), global positioning system (GPS), Galileo, and BeiDou. A single-to-differential wideband input-matched noise-canceling low-noise amplifier (LNA) is proposed to avoid the external balun and matching components. An on- chip fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> phase-locked loop (PLL) with a single voltage-controlled oscillator (VCO) generates the required local oscillator (LO) frequencies. A dc offset correction circuit is proposed in the variable gain amplifier (VGA) to avoid signal saturation. Fabricated in 65-nm CMOS technology, the receiver draws a current of 38.35 mA from a 1.2-V supply while providing a maximum gain of 101.72 dB with a programmable gain of 53.53 dB and a minimum noise figure (NF) of 3.8 dB. The receiver occupies an active die area of 1.96 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , including the I/O padring with ESD protection.
Published Version
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