Abstract
Schottky junction reconfigurable FETs suffer from limited output currents to drive the following stages, jeopardizing their viability for high-end applications. This drawback becomes dramatic at low voltages. In this work, an analogous novel low-bias reprogrammable device is presented. It features a dual PN doping at source and drain which improves the driving current density thanks to the presence of both electron and hole reservoirs within the same structure. 3D-TCAD results for this innovative device on advanced Silicon-on-Insulator technology are presented and compared with traditional reconfigurable FETs and CMOS structures.
Highlights
Reconfigurable Field-Effect Transistors (R-FET) [1] are being currently studied to implement circuits with custom on-the-fly logic functions [2], [3]
TCAD RESULTS Figure 2 depicts the DC |ID(VCG)| characteristics for all the test devices. Note that both Schottky and dual doping (DD) R-FETs exhibit bipolar behavior by adjusting the polarity-gate bias (Fig. 2a and b) which demonstrates the feasibility of employing the dual PN doped device for in-situ reconfigurable logic
The Schottky RFET exhibits a non-traditional dependence on the source-drain length due to the carrier availability at the source side
Summary
Reconfigurable Field-Effect Transistors (R-FET) [1] are being currently studied to implement circuits with custom on-the-fly logic functions [2], [3]. Injection from BEOL access contacts is ensured thanks to the high S/D doping that narrows the depletion region at the metal-semiconductor interface and allows easy carrier flow in both directions at any bias by tunneling [8], behaving as an ohmic contact In this regard, the difference with Schottky R-FETs is that DD R-FETs feature a tunneling barrier-width that is always very thin and does not depend on any terminal bias. It should be highlighted that the device operation principles do not require perfect shallow N-P junctions at S/D (as will be shown later), i.e., the N and P doping profiles at source (or drain) might be spaced to comply with the manufacturing process (see Fig. 1e) This device concept can be extended to any device geometry and number of polarity/control gates, e.g. 2-gates nanowires [1] or 2-gates planar FD-SOI [4]
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