Abstract
A high voltage (HV) CMOS process has been developed. This process allows one to easily create junction isolated HVCMOS structures on the same chip with low voltage (LV) CMOS structures. The HV structures, which are realized in a 3.5µm CMOS technology were designed for and achieved 100V operation. The process allows for the isolation of LV and HV devices and circuits. The technology is suited for applications which require the marriage of LV analog and digital signal processing and control circuitry with HV output buffers and drivers.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
