Reconfigurable Cell Research Articles

A Transformable Manufacturing Concept for Low-Volume Aerospace Assembly

This paper presents a vision for a transformable manufacturing system based on reconfigurable and adaptive intelligent technologies, anchored in the description of a real automation cell demonstrating the assembly of various aircraft structures. This production environment developed by the University of Nottingham is a new reconfigurable production environment for the complete manufacturing of high-accuracy high-complexity low-volume aerospace products. This agile reconfigurable cell can accommodate multiple product variants and families which ensures that the capital invested in fixturing is not tied to one application. By compressing the assembly of an aircraft wing structure into a single automated cell, the Future Automated Aircraft Assembly Demonstrator features a flexible, holistic, and context-aware solution that includes automated positioning, drilling, and fastening processes. The assembly cell is based on industrial robots for the handling of aircraft components while an intelligent metrology and control system monitors the cell and ensures that the operations carried out are safe and adhere to the tight tolerances required. These modules are integrated into a single, standardised interface requiring only one operator to control the cell. Performance analyses have shown that, using the reconfigurable production environment described hereafter, an assembly part location accuracy better than ±0.1 mm can be achieved.

Highly Versatile Coplanar Waveguide Line With Electronically Reconfigurable Bandwidth and Propagation Characteristics

This paper describes a coplanar waveguide coupled to two split-ring resonators that, in turn, are loaded with two different reactive elements. By these means, balanced composite right/left-handed-like (CRLH-like) and also dual balanced CRLH-like (D-CRLH-like) responses can be obtained with the same structure showing opposite propagation characteristics. This behavior is achieved by simply varying one of the reactive elements, i.e., the capacitive or inductive load. The physical behavior of these transmission lines has been successfully explained by means of a single equivalent circuit. Besides, the proposed transmission lines have an extended bandwidth due to the balanced nature of the structure. The bandwidth of these lines can be electronically controlled using varactor diodes reverse-biased by an external dc voltage. Thus, a reconfigurable cell with CRLH-like and D-CRLH-like propagation has been designed and manufactured. The simulated and measured results show fractional bandwidths from 0% (no transmission) to 9.3% for simulations and from 0% (no transmission) to 8.7% for measurements. Undoubtedly, these new proposed transmission lines will be useful for designing reconfigurable devices that can be used in future communication systems such as radar, wireless applications, global positioning systems, or radio-frequency identification systems, among others.

Equivalent circuit of a reconfigurable triple‐slot reflectarray cell

This paper presents an equivalent model for a multiple-resonance reflectar-ray cell. It allows predicting the different phase-states of the cell from only a very few full-wave simulations. Demonstrations are first given for a passive cell where different geometrical parameters are varied. Then, the approach is generalized to a reconfigurable cell. Finally, a canonical reflectarray with a steered beam has been synthesized in order to illustrate the capabilities of the proposed equivalent circuit.

Frequency Agile Radial-Shaped Varactor-Loaded Reflectarray Cell

An equivalent circuit approach is adopted in this paper to analyze a novel varactor loaded phasing line, specifically designed to improve the frequency agility fea- tures of reconfigurable aperture-coupled reflectarray cell, through the use of a couple of microstrip radial stubs. The proposed analysis method is fruitfully implemented to per- form a fast and preliminary investigation on the improve- ments provided by the radial shaped phasing line in terms of frequency agility of the reflectarray unit cell. The method is adopted to compare frequency performances of radial and linear phasing line geometries, allowing to effectively demonstrate the radial line geometry contribu- tion to the enhancement of the unit cell frequency perfor- mances.

Reconfigurable planar metamaterial unit cell

A new reconfigurable metamaterial unit cell is introduced. DC-biased controlled PIN diodes are embedded in the structure of this unit cell so that its configuration can be controlled by switching the diodes. The presented unit cell operates in two different modes. In the first mode, which is called the horizontal mode, the unit cell shows an effective permittivity and permeability close to one which leads to a refractive index around 1, whereas at the other mode, which is called vertical configuration, it possesses a double positive behaviour for the constitutive parameters and shows a refractive index of 2. Both modes are simulated using a lumped-element model for the embedded PIN diodes and the constitutive parameters are extracted using a well-known algorithm. To validate the results, the unit cell is fabricated and the free-space method is used to measure the S-parameters of the unit cell. This unit cell will be used in advanced antenna applications.

A Literature Survey on Reconfigurable Industrial Robotic Work Cells

As the unpredictability of market needs and the mass customization trends increase, employing reconfigurable industrial robotic work cells becomes a viable solution for manufacturers. A reconfigurable manufacturing system is a system designed for a quick change in structure, both in hardware and software, in order to rapidly adjust production capacity and functionalities. However, the approach is quite general; a simple search within scientific literature, patent databases or the world-wide-web returns thousands of results, covering a time period from the 80s to date. Among the results, different approaches on reconfigurable industrial robotic work cell implementations can be easily noticed. This paper surveys the literature in reconfigurable industrial robotic work cells, aiming to identify, besides the most important approaches on this topic, also performance criteria associated to robotic workcell reconfigurability and means of measuring the reconfigurability degree of such cells. The survey also aims to identify command and control architectures used to achieve various levels of reconfigurability. The survey was conducted by using a specific search methodology, which is also presented in the paper.

Tunable directivity in metamaterials with reconfigurable cell symmetry

We introduce a strategy to attain reconfigurable, highly focused, subwavelength wave patterns in cellular metamaterials via electromechanical tuning of their microstructures. The metamaterial cells feature a population of auxiliary microstructural elements instrumented with piezoelectric patches connected to negative capacitance shunting circuits. By tuning the circuital characteristics of selected subsets of shunts, we relax the symmetry of the cell material property landscape, thus affecting the global directivity and enabling a plethora of wave manipulation capabilities. The acoustic reconfiguration is decoupled from other mechanical functions and is carried out without affecting the shape or the static properties of the host cellular structure.

Multi-Level Mapping of Nanocomputer Architectures Based on Hardware Reuse

In this paper, we study the problem of mapping large applications onto hierarchical architectures based on novel nanodevices. We combine both intellectual property (IP) reuse and multi-level mapping concepts in order to cope with application complexity and reduce circuit design time. In this context, we introduce an “O-cycle” design flow that exploits the IP reuse concept for the development and further reuse of hardware component libraries through recursive multi-level mapping. The proposed mapping method chooses among different power and delay characteristics of reconfigurable logic cells that vary depending on cell internal function, e.g., NAND, OR, etc. This allows the whole system to be optimized to lower power consumption, critical path delay and area. Experimental results demonstrate 31% of power reduction for systolic array and 42% of critical path delay improvement for the “Butterfly” topology. A side-by-side comparison with existing algorithms reveals 49% and 15% reduction in area and critical path delay, respectively.

A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing

This paper presents a heterogeneous reconfigurable cell array, designed for high-throughput baseband processing of multiple-input multiple-output (MIMO) systems. To achieve high performance and energy efficiency while retaining high flexibility, the proposed architecture adopts heterogeneous and hierarchical resource deployments. Additionally, extensive vector computation enhancements and flexible memory access schemes are employed to better support MIMO signal processing. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 ${rm mm}^{2}$ core area and is capable of running at 500 MHz. For illustration, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and hard-output data detection, of a 4 $times$ 4 MIMO processing chain in a 20 MHz 64-QAM 3GPP long term evolution advanced (LTE-A) downlink are mapped and processed in real-time. Implementation results report a maximum throughput of 367.88 Mb/s with 1.49 nJ/b energy consumption. Compared to state-of-the-art designs, the proposed solution outperforms programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of efficiency to that of ASICs. (Less)

Morphosynthesis method for designing the reconfigurable analog cell of a semicustom analog-digital VLSIC with an array structure

Approaches to constructing analog reconfigurable cells of integrated circuits with an array structure are discussed. A morphological method for synthesizing an analog reconfigurable cell and the criteria for estimating its efficiency are proposed. The design and electric circuit of the reconfigurable cell are developed and the results of circuit simulation are presented.

Interchangeable Range of Ozone Concentration Simulation for Low Cost Reconfigurable Brass Gas Cell

Ultraviolet absorption spectroscopy is reliable for ozone concentration measurement. Concentration range and optical path length are inversely related based on theoretical calculation and observation of previous work. However, gas cells for ozone application are typically not expandable. In addition, they incur cost for custom fabrication. Here we design a reconfigurable brass gas cell that may interchange optical path length between 5.6 cm and 10.8 cm. Components are available at low cost, easy to joint and ready to use. Theoretical background and gas cell structure are discussed. Practical transmittance values between e-0.65 and e-0.05 are proposed for theoretical calculation of concentration via Beer-Lambert law. The concentration values are used in SpectralCalc.com gas cell simulation to obtain transmittance. Both approaches yield comparable result. Simulation result shows concentration range of 5.6 cm optical path length gas cell (31.82 ppm to 413.67 ppm) is wider than concentration range of 10.8 cm optical path length gas cell (16.50 ppm to 214.49 ppm). Simulation condition is at transmittance from 0.5291 to 0.9522, sampling wavelength 253.65 nm, temperature 300 K and pressure 1 atm. Thus, we strongly recommend short optical path length gas cell (5.6 cm) for wide range of concentration measurement (31.82 ppm to 413.67 ppm).

A dynamically reconfigurable cell array for software-defined radio

The reconfigurable cell array (RCA) architecture and its implementation are presented in this article. A distinctive feature of this architecture is its dual mode of operations. A reconfigurable cell in this array can operate in either blocking mode or non-blocking mode. This makes it suitable for efficient dataflow computation. This architecture is designed for high-throughput applications of software-defined radio (SDR) using fully pipelined and wavefront computation with fast dynamic reconfiguration. The RCA is part of a SDR chip and is responsible for the high-throughput, intermediate-frequency processing such as digital up and down conversion. In addition to the processing cells, the RCA also includes finite-state machine controllers for data stream management and distributed memory elements for stream data storage. The RCA, when combined with the programmable digital signal processor array, forms a powerful system for the SDR.

High-Efficiency Customized Coarse-Grained Dynamically Reconfigurable Architecture for JPEG2000

This brief presents an efficient implementation of JPEG2000 encoding algorithm based on an architecture consisting of a coarse-grained dynamically reconfigurable instruction cell array and an embedded advanced RISC machine core. In this implementation, different tasks within the JPEG2000 encoding algorithm are allocated with proper computational resources to achieve high throughput. The proposed architecture is dynamically reconfigured for different tasks during the encoding process. Simulation results demonstrate that the proposed architecture provides a throughput of up to 52.1 f/s (or 19.18 ms/frame) to encode a 256 × 256 standard Lena test image. Compared with various digital signal processor & very long instruction word-based JPEG2000 solutions, the proposed architecture provides significant advantages in terms of throughput and energy consumption.

Functions classification approach to generate reconfigurable fine-grain logic based on Ambipolar Independent Double Gate FET (Am-IDGFET)

Am-IDGFET is a new family of particular devices in view of the fact that it associates three benefits: (i) it is usually a 1-D electronic device (CNT or SiNW), meaning high mobility, achievable current density and high ION/IOFF ratio; (ii) Independently controlled gates which offers the device extra logic options; (iii) ambipolar behaviour opens the way for N- and P-type polarities in the same device via its back gate. The creativity of this work consists of looking at this new class of emerging technology as an opportunity for new design paradigms with no equivalent counterparts in CMOS technology. Nevertheless, to build a feasible and complete picture of ambipolar logic, innovative design approaches and tools are required. In this paper, we exploit functional classification, a powerful tool for the construction and analysis of Boolean functions, to build reconfigurable logic blocks by defining a hierarchical correlation between structures of functions classes with ambipolar devices. We demonstrate how this approach enables us to build Am-I DGFET-based n-input reconfigurable cells. Several dynamically reconfigurable 2-inputs logic cells with partial and full functionality are designed in this paper. We evaluate the performances of circuits designed from this approach in a case study focused on Double Gate Carbon Nanotube FET (DG-CNTFET) technology. Simulations results show efficiency to build fine grain reconfigurable cells with partial functionality. In the case of 9-functions reconfigurable cell, an improvement of 1.8X in terms of power delay product (PDP) is proved when compared to a CMOS-16nm technology. Fewer control signals are required and the area is reduced by 35% over CMOS technology.

Tabu Search-Based Formation of Reconfigurable Manufacturing Cells

In order to make manufacturing system to adapt to the rapidly changing global market environment, Reconfigurable Manufacturing Cells (RMCs) based on balanced distribution of machines function were presented. Firstly, Similarity Coefficient Method (SCM) was used to cluster some parts to form part families which are the foundation of RMC. Then, a mathematical optimization model was set based on the workshop layout whose functional characteristics are balanced distribution. Tabu Search (TS) algorithm was designed to solve the selection problem of process routes. In the algorithm, a recycled search method was used to generate an initial feasible solution, and then the method of swapping adjacent elements was used to generate neighborhoods. Finally, software MATLAB was used to realize the algorithm, and a case study of simulation was used to verify the feasibility and effectiveness of the algorithm.

Generation of a Reconfigurable Logical Cell Using Evolutionary Computation

In nature, an interesting topic is about how a cell can be reconfigured in order to achieve a different task. Another interesting topic is about the learning process that seems to be a trial and error process. In this work, we present mechanisms about how to produce a reconfigurable logical cell based on the tent map. The reconfiguration is realized by modifying its internal parameters generating several logical functions in the same structure. The logical cell is built with three blocks: the initial condition generating function, the tent map, and the output function. Furthermore, we propose a reconfigurable structure based on a chaotic system and an evolutionary algorithm is used in order to tune the parameters of the cell via trial and error process.

Iterative algorithms for part grouping and loading in cellular reconfigurable manufacturing systems

A reconfigurable manufacturing system (RMS), one of state-of-the-art manufacturing system technologies, is the one designed at the outset for rapid changes in its hardware and software components in order to quickly adjust its production capacity and functionality in response to market or system changes. In this study, we consider a cellular RMS with multiple reconfigurable machining cells (RMCs), each of which has numerical control machines, a setup station, and an automatic material handling and storage system. Each machine within the RMC has an automatic tool changer and a tool magazine of a limited capacity. Two important operational problems, part grouping and loading, are considered in this study. Part grouping is the problem of allocating parts to RMCs, and loading is the problem of allocating operations and their cutting tools to machines within the RMC. An integer programming model is suggested to represent the two problems at the same time for the objective of balancing the workloads assigned to machines. Then, due to the complexity of the problem, we suggest two iterative algorithms in which the two problems are solved repeatedly until a solution is obtained. Computational experiments were done on various test instances and the results are reported.

Evaluation of the logistic model of the reconfigurable manufacturing system based on generalised stochastic Petri nets

To reveal the influence on system performance by the logistic model of reconfigurable manufacturing system (RMS), the generalised stochastic Petri nets (GSPN) modular modelling approach is presented in this paper. It is based upon the characteristics of a bottleneck service. According to this approach, the bottleneck service in the production process is found first. By corresponding different resources in the service to different modules of the GSPN, the module is reconfigured. The analysis of the model using the Markov chain is hereby presented, as is the average utilisation factor of RMS. Following this, the production capacity of different products and the average productivity of reconfigurable manufacturing cells (RMCs) are discussed.

Electric double‐layer capacitor module with series‐parallel reconfigurable cell voltage equalizers

AbstractWhen electric double‐layer capacitors (EDLCs) are connected in series, a cell voltage imbalance occurs due to nonuniform cell properties. Cell voltage imbalance should be minimized to prolong cycle lives and maximize the available energy of cells. In this study, we propose a series‐parallel reconfigurable cell voltage equalizer that is considered suitable for energy storage systems using EDLCs instead of traditional secondary batteries as the main energy storage sources. The proposed equalizer requires only EDLCs and switches as its main circuit elements, and it utilizes EDLCs not only for energy storage but also for equalization. An equivalent circuit model using equivalent resistors that can be regarded as an index of equalization speed is developed. Current distribution and cell voltage imbalancing during operation are quantitatively generalized. Experimental charge–discharge tests were performed on the EDLC modules to demonstrate the performance of the cell voltage equalizer. All the cells in the modules could be charged/discharged uniformly even when a degradation‐mimicking cell was intentionally included in the module. The resultant cell voltage imbalances and current distributions were in good agreement with those predicted by mathematical analyses. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 181(4): 38–50, 2012; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.21287

Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation

In this article, we present a constraint programming approach for solving hard design problems present when automatically designing specialized processor extensions. Specifically, we discuss our approach for automatic selection and synthesis of processor extensions as well as efficient application compilation for these newly generated extensions. The discussed approach is implemented in our integrated design framework, IFPEC , built using Constraint Programming (CP). In our framework, custom instructions, implemented as processor extensions, are defined as computational patterns and represented as graphs. This, along with the graph representation of an application, provides a way to use our CP framework equipped with subgraph isomorphism and connected component constraints for identification of processor extensions as well as their selection, application scheduling, binding, and routing. All design steps assume architectures composed of runtime reconfigurable cells, implementing selected extensions, tightly connected to a processor. An advantage of our approach is the possibility of combining different heterogeneous constraints to represent and solve all our design problems. Moreover, the flexibility and expressiveness of the CP framework makes it possible to solve simultaneously extension selection, application scheduling, and binding and improve the quality of the generated results. The article is largely illustrated with experimental results.