Reconfigurable Cell Research Articles

Technology Remapping Approach Using Multi-Gate Reconfigurable Cells for Post-Mask Functional ECO

Technology Remapping Approach Using Multi-Gate Reconfigurable Cells for Post-Mask Functional ECO

A Reconfigurable 7T SRAM Bit Cell for High Speed, Power Saving and Low Voltage Application

The decreasing operational voltage and scaled technology node for memory designing has widened the gap between two crucial parameters for an SRAM – delay and power. As the demand for internet of things is increasing, the need for round the clock connectivity is increasing. This mandates designing a cell with a capability to switch between low power and high speed operation. Thus, this paper presents the design of dual mode operational 7T cell that can switch between single port and dual port configuration. The proposed reconfigurable cell can operate as single port or dual port cell single ended 7T cell. The reconfigurability in the cell is realized using control signals. The noise stability of the bit cell is obtained to be 333, 333, and 470 mV for read, hold, and write modes, respectively. The robustness of the cell against temperature variation, process variation and voltage variation is also analyzed. The performance variation in each parameter will not have a dramatic impact as it is within manageable limit. Its write time is 0.14 ns, while 5 ps are required for a successful read operation. The dual port configuration of the cell supports pipelining and thus operates faster than its single port configuration.

Reconfigurable regular expression matching architecture for real-time pattern update and payload inspection

Regular expression (regex) matching is an integral part of deep packet inspection (DPI), but its efficiency becomes a question due to low performance. For regex matching (REM) acceleration, FPGA-based solutions have emerged to maximize parallelism by processing multiple regex patterns concurrently. However, even though they significantly accelerate the performance, they have a critical problem that they do not support dynamic regex pattern updates in run time, which is the key functionality along with frequently altered signatures to cover newly identified vulnerabilities. Hence, we present Reinhardt, a new reconfigurable hardware architecture for REM. Reinhardt introduces new FPGA blocks, called reconfigurable cells, that form regex patterns in hardware, enabling real-time regex pattern update and match in run time while providing high performance. With the prototype of Reinhardt on NetFPGA-SUME, our evaluation shows that Reinhardt updates hundreds of regex patterns within a second and performs REM at up to 10 Gbps throughput (max. hardware bandwidth) with the constant latency. Our case studies also show that Reinhardt can operate in multiple modes (e.g., as a standalone NIDS/NIPS or as the REM accelerator for them).

Light‐Responsive Bilayer Cell Culture Platform for Reversible Cell Guidance

In vivo, cells are surrounded by a constantly changing microenvironment, which regulates many cell functions such as differentiation, migration, and cell death. Stimuli‐responsive biomaterials aim to mimic this interaction between cells and extracellular matrix in vitro. However, reproducing dynamic signaling noninvasively without affecting the cell viability remains a challenge. Herein, a dynamic cell culturing platform consisting of a light‐responsive azobenzene molecular glass film and a protective polydimethylsiloxane (PDMS) coating is developed. By tuning the PDMS layer thickness, surface relief gratings (SRGs) can be efficiently photoinscribed on the platform surface. The SRGs can also be erased with light in the presence of PDMS, i.e., the topography can be reversibly photomodulated. The inscribed SRGs can guide epithelial cell orientation along the topography. The erasure parameters are targeted toward cell culturing environment, enabling experiments with live cells. Finally, the photoresponsive platform is patterned with proteins by microcontact printing, allowing its biofunctionalization and the combination of microtopography and protein patterns. This study paves the way for using reconfigurable cell culture platforms for the dynamic control of cell–material interactions. The PDMS coating has potential to protect underneath material, broadening the spectrum of possible materials for dynamic cell culture platforms.

A New Reconfigurable Filter Based on a Single Electromagnetic Bandgap Honey Comb Geometry Cell

This work presents a new unit cell electromagnetic bandgap (EBG) design based on HoneyComb geometry (HCPBG). The new HCPBG takes a uniplanar geometry (UCPBG—uniplanar compact PBG) as a reference and follows similar design methods for defining geometric parameters. The new structure’s advantages consist of reduced occupied printed circuit board area and flexible rejection band properties. In addition, rotation and slight geometry modification in the HCPBG cell allow changing the profile of the attenuation frequency range. This paper also presents a reconfigurable unit cell HCPBG filter strategy, for which the resonance center frequency is shifted by changing the gap capacitance with the assistance of varactor diodes. The HCPBG filter and reconfiguration behavior is demonstrated through electromagnetic (EM) simulations over the FR1 band of the 5G communication network. Intelligent communication systems can use the reconfiguration feature to select the optimal operating frequency for maximum attenuation of unwanted or interfering signals, such as harmonics or intermodulation products.

Reconfigurable THz Metamaterial Filter Based on Binary Response for Information Processing System

Light-matter interactions between the metallic and dielectric layers along with the controlling of electromagnetic waves can create a way to develop micro-devices and moderate the functionalities for advanced applications. This study describes a new controlling technique of the plasmatic electron packet based on an electric split-ring resonator (eSRR). All numerical experiments were performed using an advanced CST electromagnetic package. The proposed metamaterial tunneled structure in this study operates using terahertz (THz) frequency spectrum as an efficient digital processing filter. The array combination of the tunneled structure consisted of three individual unit cells. Moreover, the two engineered metallic arms added to the tunneled structure exhibited two peak resonances and one passband frequency region. A large evanescent field was produced to enhance the wave-metal interactions with the presence of a metal-dielectric micro-tunnel. The intensity of the electromagnetic wave-metal interactions was encoded to binary 0 and 1 for information encoding purposes. As a result, the reconfigurable micro-unit cell metamaterial tunneled structure was able to effectively control the electric field and allow electron packets to be digitally encoded for the information processing system.

Double-String Battery System with Reconfigurable Cell Topology Operated as a Fast Charging Station for Electric Vehicles

This paper introduces a novel design of an electric vehicle (EV) fast charging station, consisting of a battery energy storage system (BESS) with reconfigurable cell topology. The BESS comprises two battery strings that decouple the power flow between EV and grid, to enable charging powers above the grid capacity. The reconfigurable design is achieved by equipping the battery cells with semiconductor switches and serves two main purposes. First, it aims at solving cell unbalance issues to increase safety, reliability, and lifetime of the battery. Second, it enables the BESS to actively control the EV charging process by changing its cell configuration in a real-time fashion, making a DC-DC converter redundant. The paper presents a modelling approach that captures the reconfigurable design including the controlling algorithm used for cell engagement. The simulation results show that the BESS is able to fulfil the EV request with sufficient accuracy for most of the fast charging process. However, the switching of cells leads to variations in the charging current that can potentially exceed the tolerance band defined in IEC61851-23. Therefore, complementary measures are suggested to achieve a suitable current control during all phases of the charging process. The estimated BESS efficiency during the EV fast charging process is 93.3%. The losses caused by the reconfigurable design amount to 1.2% of the provided energy. It is demonstrated that the proposed design has a competitive efficiency compared to a battery buffered fast charging station with DC-DC converter.

Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture

Row Parallel Coarse-Grained Reconfigurable Architecture (RPCGRA) has the advantages of maximum parallelism and programmable flexibility. Designing an efficient algorithm to map the diverse applications onto RPCGRA is difficult due to a number of RPCGRA hardware constraints. To solve this problem, the nodes of the data flow graph must be partitioned and scheduled onto the RPCGRA. In this paper, we present a Depth-First Greedy Mapping (DFGM) algorithm that simultaneously considers the communication costs and the use times of the Reconfigurable Cell Array (RCA). Compared with level breadth mapping, the performance of DFGM is better. The percentage of maximum improvement in the use times of RCA is 33% and the percentage of maximum improvement in non-original input and output times is 64.4% (Given Discrete Cosine Transfor 8 (DCT8), and the area of reconfigurable processing unit is 56). Compared with level-based depth mapping, DFGM also obtains the lowest averages of use times of RCA, non-original input and output times, and the reconfigurable time.

Fixed Frequency Beam-Scanning HMSIW-Based Leaky-Wave Antenna Composed of Circular Slots in V-Shape Configuration

A new reconfigurable slotted antenna is presented in this manuscript. The proposed antenna is realized on a half-mode substrate integrated waveguide (HMSIW). The beam-steering is achieved using embedded varactor diodes in circular cells. Sweeping the bias voltage causes variations of the phase constant, which leads to the fixed frequency beam-scanning. Each reconfigurable cell includes a circular slot at the top plate and varactor switch, DC block, and RF block at the backside of the structure. The operating frequency is chosen as 28.5 GHz in the support of the upcoming 5G mm-wave communications systems. The proposed antenna beam scans 29° of space by switching among different states at 28.5 GHz. The length, width, and height of the antenna are 67 mm, 48 mm, and 0.32 mm, respectively. The proposed antenna’s main novelties are compactness and electronic beam-scanning capability using a single switch per cell. The measured peak realized gain and sidelobe level (SLL) at 28.5 GHz are 8.2 ± 0.6 dBi and 5 dB, respectively. While the impedance bandwidth of the proposed antenna is 1.5 GHz. A good agreement between measured and simulated results is observed. The discrepancies are investigated through a sensitivity analysis. Fixed frequency beam-scanning capability, compactness, simplicity of the assembly, backward radiation, and slight gain variation of the proposed antenna make it a suitable candidate for blind-spot monitoring and 5G vehicle to everything (V2X) communications.

Real-Time Mode Switching and Beam Scanning of High-Gain OAM Waves Using a 1-Bit Reconfigurable Reflectarray Antenna

A reconfigurable electromagnetic surface has been studied to realize the adjustable orbital angular momentum (OAM) beams for real-time wireless communication and dynamic target detection in the future. OAM mode switching realized by many previous designs suffers from low gains without OAM beam scanning. In this article, a 1-bit reconfigurable reflectarray antenna is designed, fabricated, and tested for the real-time control of OAM mode switching and large-angle vortex beam scanning in three-dimensional space. The proposed reflectarray surface is composed of 1-bit electronically reconfigurable cells, and the size is 24 λ × 24 λ with 2304 units. The reconfigurable element is designed by using a radiation patch loading a PIN diode with effective control of two states, “ON” and “OFF”, for the demand of 180° phase difference. The reflectarray surface can be assigned to a code sequence of 0 or 1 by the Field-Programmable Gate Array (FPGA) in real time. Henceforth, the coding surface can dynamically control the generation of high-gain OAM beams, where only the optimized phase distributions on the surface need to be changed according to demand. To verify the concept, a large-scale reflectarray surface is fabricated and measured with an oblique feed at 15°. Different OAM-carrying phase distributions for different OAM beam states are calculated and tested. The test results show that the OAM mode switching between l = 1 and l = 2 is realized, and other variable modes such as l = 3 or l = 5 can also be achieved by modifying the phase encoding sequence. Furthermore, the direction of the vortex beams can be accurately controlled with gains over 20 dBi, and the large-angle vortex beam scanning is verified. Therefore, all results demonstrate that the proposed 1-bit reconfigurable reflectarray is efficient for the regulation and control of OAM-carrying beams for the demand of real-time dynamic wireless communications in the future.

Construction of a Cost-Effective Phased Array Through High-Efficiency Transmissive Programable Metasurface

Programmable metasurfaces have shown great potential in the areas of low-complexity phase array systems in comparison with the conventional phased array antennas. In this document, a 1-bit transmissive programable metasurface with high efficiency is proposed for the cost-effective beam-steering phased array. The designed transmissive metasurface is made up of reconfigurable cells with perfect 1-bit phase tuning and less transmission losses. Through dynamically programming the 1-bit code distributions of the metasurface, real-time scanning pencil beams in desired directions can be created.

Area and delay efficient GDI based accuracy configurable adder design

Adders are one of the basic fundamental critical arithmetic circuits in a system and their performances affect the overall performance of the system. Traditional n-bit adders provide precise results, whereas the lower bound of their critical path delay of n bit adder is Ὠ(log n). To achieve a minimum critical path delay lower than Ὠ(log n), many inaccurate adders have been proposed. These inaccurate adders decrease the overall critical path delay and improve the speed of computation by sacrificing the accuracy or predicting the computation results. In this work, a fast reconfigurable approximate ripple carry adder has been proposed using GDI (Gate Diffusion Logic) passing cell. Here, GDI cell acts as a reconfigurable cell to be either connected with the previous carry value or approximated value in an adder chain. This adder has greater advantage and it can be configured as an accurate or inaccurate adder by selecting working mode in GDI cell. The implementation results show that, in the approximate working mode, the proposed 64-bit adder provides up to 23%, 34% and 95% reductions in area, power and delay, respectively compared to those of the existing adder.

Sequential optimisation of reconfigurable machine cell feeders and production sequence during lean assembly

ABSTRACTThis paper presents a manufacturing model for integrating reconfigurable machine cells as feeders of components to a multi-product assembly line exhibiting a prominent lean characteristic; synchronisation with Takt time. Two mathematical formulations in the form of combinatorial optimisation problems are developed to identify the best reconfiguration for the machines by optimum selection of the modules in the cells to minimise the total error with Takt time and then the optimum sequence of assembling the products to minimise the total reconfiguration time and effort. An elitist genetic algorithm (GA) meta-heuristic is employed twice in succession to search the optimal solutions for both the minimisation problems. The best machine configuration found from the first search is utilised further to identify the optimal assembly sequence. A hypothetical data set representing the features and parameters of the model in conformance with any typical mixed-model assembly is presented for illustration of computational procedure. Synchronisation among machine cells and tardiness are considered as performance evaluation measures to validate the effectiveness of the proposed model.

One-dimensional beam-steering Fabry–Perot cavity (FPC) antenna with a reconfigurable superstrate

AbstractIn this work, a new reconfigurable discrete 1D beam-steering Fabry–Perot cavity antenna with enhanced radiation performance is presented. It consists of a probe-fed patch antenna printed on the ground plane and a reconfigurable metasurface acting as the upper partially reflective surface to realize beam steering. By utilizing 6 × 6 proposed reconfigurable unit cells on the superstrate, the beam-steering angle can be effectively enhanced from ±7° to ±17° with fewer active elements and a much simpler biasing network. The proposed antenna was fabricated to validate the feasibility. Good agreement between the simulated and measured results is achieved. Moreover, the measured realized gains are over 11 dBi with a gain variation from the boresight direction to the tilted direction <0.2 dBi.

An approach for the robust design of a reconfigurable assembly cell with 7-axis robot

ABSTRACTThe increasing variety of products and the variability of the demand are pushing manufacturing companies in a challenging and competing environment. These trends affect many industrial sectors, including the automotive one, impacting the whole supply chain, including the production of spare parts. The automotive spare part’s market is aimed at providing replacing parts during the whole life cycle of cars. As the design of cars becomes more and more sophisticated, producing spare parts requires complex production processes, a wide range of different technologies and the need to cope with different materials. In this context, the design of assembly systems and proper management policies have a considerable importance for the competitiveness of spare parts suppliers. In this paper, a configuration approach is proposed, to select a robust design solution for a reconfigurable assembly cell. The solution consists of an initial configuration together with a set of alternative reconfiguration plans to cope with the intrinsic uncertainty of the spare part manufacturing requirements. An innovative reconfigurable assembly cell architecture is exploited, while robustness is pursued by minimising a function of the risk associated with investment and operational costs of the assembly cell. The viability of the proposed approach is demonstrated through the application to an industrial case.

Assessment of Alternative Manufacturing Work Cells for SMEs

Globally small and medium-sized manufacturing enterprises (SMEs) are confronting serious challenges due to dynamic market demands. In pursuit of such situations they opt to be lean and flexible. Their demand have numerous varieties in product geometry and manufacturing processes. To cater such demand among the several existing strategies, reconfigurable manufacturing work cell (RWC) is the most prudent choice owing to its numerous benefits. This study offer an assessment lens to those who look for reconfiguration of their manufacturing setup. It is prudent to consider various RWC alternatives while wanting to reconfigure existing configuration change from time to time. The paper proposes a grey relational approach coupled with fuzzy analytical hierarchy weight to evaluate alternative RWCs. The simulation platform is adopted to exhibit performance of each RWC. The developed approach is to aid decision makers in identifying the most suitable RWC for the SME.

Online placement and scheduling algorithm for reconfigurable cells in self-repairable field-programmable gate array systems

Most of the high-end very-large-scale integration- (VLSI-) based systems use a field-programmable gate array (FPGA) as their core component. As the complexity of systems increases, the chances of fault occurrence also increase. For systems that are part of safety-critical and mission-critical applications, even a single fault can result in entire mission failure. Fault tolerance techniques need to be installed in such systems to ensure reliable, prolonged operation in spite of fault occurrence. The level of fault tolerance exhibited in nature is very remarkable. Scientists are trying to reach that level of fault tolerance in the electronics world as well, which is not always completely acquirable. Basically, fault tolerance in an FPGA is achieved by the use of spare modules, which leads to high area overheads and routing complexity. The higher the number of faults to be handled, the greater the number of spares that will be required. Partial reconfiguration has always been a proven technique to improve the efficiency and flexibility of FPGAs. This paper discusses a multiple-fault repair algorithm for FPGA-based reconfigurable systems, using dynamic runtime partial reconfiguration, in order to relocate faulty modules. Three variants or cases of repair using the algorithm are discussed and demonstrated, namely, placement with the best resource utilization, placement with the least routing overhead, and a case to generate continuous free space for the relocation of a faulty module. The main advantage of the algorithm is its flexibility, which means that it can be used according to user demands and system lifetime requirements. Maximum care is taken to eliminate chances of an unrepaired fault or a repair that degrades the performance of the system. The algorithm can handle multiple permanent faults with the best resource utilization and the least overheads. The performance of the algorithm is analyzed quantitatively, while a comparison is made with some previous studies in the literature to justify the algorithm efficiency.

A dynamically reconfigurable logic cell: from artificial neural networks to quantum-dot cellular automata

Considering the lack of optimization support for Quantum-dot Cellular Automata, we propose a dynamically reconfigurable logic cell capable of implementing various logic operations by means of artificial neural networks. The cell can be reconfigured to any 2-input combinational logic gate by altering the strength of connections, called weights and biases. We demonstrate how these cells may appositely be organized to perform multi-bit arithmetic and logic operations. The proposed work is important in that it gives a standard implementation of an 8-bit arithmetic and logic unit for quantum-dot cellular automata with minimal area and latency overhead. We also compare the proposed design with a few existing arithmetic and logic units, and show that it is more area efficient than any equivalent available in literature. Furthermore, the design is adaptable to 16, 32, and 64 bit architectures.

Design of smart connected manufacturing resources to enable changeability, reconfigurability and total-cost-of-ownership models in the factory-of-the-future

The fourth industrial revolution requires higher capabilities of changeability and reconfigurability (C–R) of the future factories (FoF), as well as a higher focus on business models that are based on total-cost-of-ownership (TCO) paradigm. Up to date, there are little scientific contributions to deploy C–R into TCO models, as well as to systematic plan and design manufacturing resources such as to facilitate FoF ecosystem. In order to address this issue, this paper introduces research results that show how to deploy C–R, connectivity, smartness and TCO requirements into the technical solutions of manufacturing resources of FoF. Contributions emerging from this research include an index to measure C–R capability of manufacturing resources, a model to assess economic feasibility of a FoF over its lifecycle, as well as a methodology and related tools to design smart connected manufacturing resources with embedded features to facilitate changeability and reconfigurability in a FoF. Theoretical contributions are explained through a case study of a fast reconfigurable robotic manufacturing cell. Preliminary results demonstrate that it is possible to rapid design smart connected manufacturing resources and integrate them into FoF architectures that support convertibility, integrability, modifiability, adaptability, serviceability, scalability, integration of resources from various producers, service clustering and cloud-based services.

Design and implementation of a data-driven dynamical reconfigurable cell array

The nature of dataflow computation demands the heavy flow of tokens amongst computation nodes. Traditional reduced instruction-set computer (RISC) processors are not suitable for such style computation. Devices that use long wire buses are not suitable for dataflow either. Reconfigurable computing devices (RCDs) consist of data transfer wires and computing resources. With minor modifications, reconfigurable cells can be adopted to perform dataflow computation. A reconfigurable cell array (RCA) is presented in this paper and it is suitable for dataflow computation. This cell array has a dynamic reconfigurable storage model. The distinctive features of the architecture include dataflow reconfigurable cells and reconfigurable storage. Dataflow applications can be mapped easily and effectively onto the cells. Reconfigurable storage is mainly used to manage data access and transmission. Furthermore, computation and data management are separated. Meanwhile, dynamical reconfiguration is accomplished, when some clusters of cells work in configuration mode and other clusters work in computation mode. The dataflow graphs of some algorithms are mapped onto our architecture, and the performance results are compared with those of CPU and GPU.