Multi-Level Mapping of Nanocomputer Architectures Based on Hardware Reuse

Abstract

In this paper, we study the problem of mapping large applications onto hierarchical architectures based on novel nanodevices. We combine both intellectual property (IP) reuse and multi-level mapping concepts in order to cope with application complexity and reduce circuit design time. In this context, we introduce an “O-cycle” design flow that exploits the IP reuse concept for the development and further reuse of hardware component libraries through recursive multi-level mapping. The proposed mapping method chooses among different power and delay characteristics of reconfigurable logic cells that vary depending on cell internal function, e.g., NAND, OR, etc. This allows the whole system to be optimized to lower power consumption, critical path delay and area. Experimental results demonstrate 31% of power reduction for systolic array and 42% of critical path delay improvement for the “Butterfly” topology. A side-by-side comparison with existing algorithms reveals 49% and 15% reduction in area and critical path delay, respectively.