Receiver ASIC Research Articles

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8 × 10−16, significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.

QTIA, a 2.5 or 10 Gbps 4-channel array optical receiver ASIC in a 65 nm CMOS technology

The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed the lab tests with GaAs photodiodes.

Characterization and quality control test of a gigabit cable receiver ASIC (GBCR2) for the ATLAS Inner Tracker Detector upgrade

We present the characterization and quality control test of a gigabit cable receiver ASIC prototype, GBCR2, for the ATLAS Inner Tracker pixel detector upgrade. GBCR2 equalizes and retimes the uplink electrical signals from RD53B through a 6 m Twinax AWG34 cable to lpGBT. GBCR2 also pre-emphasizes downlink command signals through the same electrical connection from lpGBT to RD53B. GBCR2 has seven uplink channels each at 1.28 Gbps and two downlink channels each at 160 Mbps. The prototype is fabricated in a 65 nm CMOS process. The characterization of GBCR2 has been demonstrated that the total jitter of the output signal is 129.1 ps (peak-peak) in the non-retiming mode or 79.3 ps (peak-peak) in the retiming mode for the uplink channel and meets the requirements of lpGBT. The total power consumption of all uplink channels is 87.0 mW in the non-retiming mode and 101.4 mW in the retiming mode, below the specification of 174 mW. The two downlink channels consume less than 53 mW. A quality control test procedure is proposed and 169 prototype chips are tested. The yield is about 97.0%.

Design and Implementation of a Digital Front-End With Digital Compensation for Low-Complexity 4G Radio Transceivers

A digital front-end with digital compensation is designed and implemented for low-complexity 4G radio transceivers targeted for wearable devices such as smart watches. The proposed digital front-end in the radio receiver consists of an anti-drooping filter, a decimation chain, a DC offset cancellation circuit, and an in-phase and quadrature estimation and compensation circuit whereas the digital front-end in the radio transmitter includes an anti-drooping filter, a root raised cosine filter, and an interpolation chain. The proposed DC offset cancellation circuit is based on both infinite-duration impulse response filter and moving average. The proposed in-phase and quadrature estimation and compensation circuit attains lower complexity with negligible performance loss, compared with an existing circuit. A systematic top-down strategy is taken to design and implement the proposed digital front-end from the algorithm level to the application-specific integrated circuit or ASIC hardware level. The inter-symbol interference in the transmitter and the receiver is analyzed and the unwanted emission in the transmitter is simulated as well. For all the seven bandwidths or modes in 3G and 4G, the digital front end receiver ASIC satisfies all the interference requirements, namely, in-band blocker, narrowband blocker, and adjacent channel selectivity requirements whereas the digital front end transmitter ASIC meets all the unwanted emission requirements, namely, spectrum emission mask, spurious emission, and adjacent channel leakage ratio requirements. The proposed multimode 4G digital front end receiver and transmitter ASICs exhibit a >40dB mean signal-to-noise ratio for all the seven modes and are implemented in a 180nm CMOS process technology.

1.28 and 5.12 Gbps multi-channel twinax cable receiver ASICs for the ATLAS Inner Tracker Pixel Detector upgrade

We present two prototypes of a gigabit transceiver ASIC, GBCR1 and GBCR2, both designed in a 65-nm CMOS technology for the ATLAS Inner Tracker Pixel Detector readout upgrade.The first prototype, GBCR1, has four upstream receiver channels and one downstream transmitter channel with pre-emphasis. Each upstream channel receives the data at 5.12 Gbps through a 5 m AWG34 Twinax cable from an ASIC driver located on the pixel module and restores the signal from the high frequency loss due to the low mass cable. The signal is retimed by a recovered clock before it is sent to the optical transmitter VTRx+. The downstream driver is designed to transmit the 2.56 Gbps signal from lpGBT to the electronics on the pixel module over the same cable. The peak–peak jitter (throughout the paper jitter is always peak–peak unless specified) of the restored signal is 35.4 ps at the output of GBCR1, and 138 ps for the downstream channel at the cable ends. GBCR1 consumes 318 mW and is tested.The second prototype, GBCR2, has seven upstream channels and two downstream channels. Each upstream channel works at 1.28 Gbps to recover the data directly from the RD53B ASIC through a 1 m custom FLEX cable followed by a 6 m AWG34 Twinax cable. The equalized signal of each upstream channel is retimed by an input 1.28 GHz phase programmable clock. Compared with the signal at the FLEX input, the additional jitter of the equalized signal is about 80 ps when the retiming logic is off. When the retiming logic is on, the jitter is 50 ps at GBCR2 output, assuming the 1.28 GHz retiming clock is from lpGBT. The downstream is designed to transmit the 160 Mbps signal from lpGBT through the same cable connection to RD53B and the jitter is about 157 ps at the cable ends. GBCR2 consumes about 150 mW when the retiming logic is off. This design was submitted in November 2019.

Development and test of the DAQ system for a Micromegas prototype to be installed in the ATLAS experiment

A Micromegas (MM) quadruplet prototype with an active area of 0.5 m2 that adopts the general design foreseen for the upgrade of the innermost forward muon tracking systems (Small Wheels) of the ATLAS detector in 2018-2019, has been built at CERN and is going to be tested in the ATLAS cavern environment during the LHC RUN-II period 2015-2017.The integration of this prototype detector into the ATLAS data acquisition system using custom ATCA equipment is presented. An ATLAS compatible Read Out Driver (ROD) based on the Scalable Readout System (SRS), the Scalable Readout Unit (SRU), will be used in order to transmit the data after generating valid event fragments to the high-level Read Out System (ROS). The SRU will be synchronized with the LHC bunch crossing clock (40.08 MHz) and will receive the Level-1 trigger signals from the Central Trigger Processor (CTP) through the TTCrx receiver ASIC. The configuration of the system will be driven directly from the ATLAS Run Control System. By using the ATLAS TDAQ Software, a dedicated Micromegas segment has been implemented, in order to include the detector inside the main ATLAS DAQ partition. A full set of tests, on the hardware and software aspects, is presented.

Clock and data recovery methods for the readout control unit 2 in ALICE TPC

The present ALICE TPC readout electronics consists of 4356 Front End Cards that are read out and controlled by a total of 216 Readout Control Units (RCUs). The RCU communicates with all sub-systems, in particular with the Timing, Trigger and Control (TTC) system, which provides each RCU with the 40.08 MHz LHC clock, which is used as a system and sampling clock in TPC readout electronics. The LHC clock and trigger data are sent over the TTC fiber using 80 Mb/s Time Division Multiplexed BiPhase Mark encoded signals. It is important to have a radiation tolerant solution to recover the clock with low jitter and with a predefined phase-offset to the LHC input clock. Presently, this is handled by the TTC receiver (TTCrx) ASIC sitting on the RCU.

Design, production, and reliability of the new ATLAS pixel opto-boards

New fiber optical transceivers, opto-boards, were designed and produced to replace the first generation opto-boards installed in the ATLAS pixel detector and for the new pixel layer, the insertable barrel layer (IBL). Each opto-board contains one 12-channel PIN array and two 12-channel VCSEL arrays along with associated receiver and driver ASICs. The new opto-board design benefits from the production and operational experience of the first generation opto-boards and contains several improvements. The new opto-boards have been successfully installed. Additionally, a set of the new opto-boards have been subjected to an accelerated lifetime experiment at 85 C and 85% relative humidity for over 1,000 hours. No failures were observed. We are cautiously optimistic that the new opto-boards will survive until the shutdown for the detector upgrade for the high-luminosity Large Hadron Collider (HL-LHC).

A Low Noise Figure 1.2-V CMOS GPS Receiver Integrated as a Part of a Multimode Receiver

This paper presents what kind of challenges are posed when a global positioning system (GPS) receiver is being added to a multiradio terminal. The GPS receiver chain is integrated as a part of a multiband and multimode receiver, designed for global system for mobile communications (GSM) and wideband code division multiple access (WCDMA). The hostile radio environment challenges in a terminal level are discussed. Especially, the modifications of the additional GPS mode to an existing receiver ASIC with minor and most necessary changes to the implementation is discussed and presented. The IC is implemented in a 0.13-mum CMOS technology without any analog options. At 1.2-V supply voltage and total power dissipation of 49 mW for the analog signal path, the proposed GPS receiver features a noise figure of 2.2 dB and an out-of-band IIP3 of +24 dBm for the worst-case test scenario, which makes it suitable to cellular handset usage in a demanding interference environment.

Pulsed time-of-flight laser radar module with millimeter-level accuracy using full custom receiver and TDC ASICs

A laser rangefinding device based on a pulsed time-of-flight distance measurement technique was constructed and tested. The aim, millimeter-level measurement accuracy with low power consumption, cost, and size, were achieved using full-custom application-specific integrated circuits in significant parts of the device, the receiver channel, and the time-to-digital converter. The accuracy of the device with a measurement time of one second and of the optomechanical head used in the measurements is at the mm-level in the case of a noncooperative target at a measurement range from 4 to 34 m and at a temperature between -10/spl deg/C and +50/spl deg/C.

A fully integrated CMOS PM radio receiver for wristwatch calibration

In this paper, a fully integrated phase modulation radio receiver ASIC is presented. The ASIC is a mixed analog and digital circuit, implemented in a 1.5-/spl mu/m CMOS technology. The only required external components are the reception antenna and a 32-kHz crystal. The radio receiver is dedicated to the 162-kHz Allouis radio transmitter. In addition to the audio information, 40-bit/s digital data are transmitted as phase modulation of the main carrier. These digital data may contain live information, such as the exact time. The presented ASIC demodulates and decodes these digital data. The principal features of this radio receiver are a low voltage supply (2.2-4.5 V), low power consumption (less than 150 /spl mu/A), a large sensitivity range (10 /spl mu/V-100 mV), and a reduced number of external components. Thanks to all of these performances, the circuit can be built in a wristwatch.

Design Methodology for a DVB Satellite Receiver ASIC

This contribution describes design methodology and implementation of a single-chip timing and carrier synchronizer and channel decoder for digital video broadcasting over satellite (DVB-S). The device consists of an A /D converter with AGC, timing and carrier synchronizer with matched filter, Viterbi decoder including node synchronization, byte and frame synchronizer, convolutional de-interleaver, Reed Solomon decoder, and a descrambler. The system was designed in accordance with the DVB specifications. It is able to perform Viterbi decoding at data rates up to 56 Mbit /s and to sample the analog input values with up to 88 MHz. The chip allows automatic acquisition of the convolutional code rate and the position of the puncturing mask. The symbol synchronization is performed fully digitally by means of interpolation and controlled decimation. Hence, no external analog clock recovery circuit is needed. For algorithm design, system performance evaluation, co-verification of the building blocks, and functional hardware verification an advanced design methodology and the corresponding tool framework are presented which guarantee both short design time and highly reliable results. The chip has been fabricated in a 0.5 µm CMOS technology with three metal layers. A die photograph is included.

Wideband compressive receiver based on advanced superconductor and semiconductor circuits

A novel compressive cryoreceiver architecture has been proposed combining analog HTS, cryoelectronic, and advanced high-speed GaAs and high-speed/low-power SOI CMOS semiconductor technologies. The proposed receiver will rival the sensitivity of narrowband receivers while providing unprecedented wideband instantaneous frequency coverage with very small size, weight, and power requirements. Future developments will extend the bandwidth capability. HTS tapped-delay-line chirp filters are the enabling technology for instantaneous bandwidths greater than 1 GHz. The filters support dispersive delays as long as 40 ns and time-bandwidth products in excess of 100 using a bonded/thinned-wafer technique to fabricate YBa/sub 2/Cu/sub 3/O/sub 7-/spl part// stripline structures on 125-/spl mu/m-thick, 5-cm-diam LaAlO/sub 3/ substrates. The filters have produced better than -18-dB error sidelobes in a receiver configuration. Preliminary work toward SOI CMOS receiver ASICs is reported. These ASICs will perform pulse data thinning, and binary integration functions. Requirements for A/D converters are discussed.

Receiver ASIC for timing, trigger and control distribution in LHC experiments

An ASIC receiver has been developed for the optical timing, trigger and control distribution system for LHC detectors. It is capable of recovering the LHC reference clock and the first-level trigger decisions and making them available to the front-end electronics properly deskewed in time. The timing receiver is also capable of recognising individually addressed commands to provide some slow control capability. Its main functions include post-amplification of the signal received from a photodetector-preamplifier, automatic gain control, data/clock separation, demultiplexing of the trigger and data channels and programmable coarse/fine deskewing functions. The design has been mapped into a standard 1 /spl mu/m CMOS process with all the analogue and timing critical functions implemented in full custom. The jitter measured on the recovered clock is less than 100 ps for input optical powers down to -25 dBm. The time deskewing functions allow the commands and the first level trigger accept signal to be phase shifted up to a maximum of sixteen clock cycles in steps of 0.1 ns.