Real-time Embedded Applications Research Articles

RFSOD: a lightweight single-stage detector for real-time embedded applications to detect small-size objects

RFSOD: a lightweight single-stage detector for real-time embedded applications to detect small-size objects

Hardware support in a middleware for distributed and real-time embedded applications

One of the main challenges in the development of tools and methodologies for a multiprocessor realtime embedded system is to reuse already developed software, but at the same time obtaining low memory footprint, low energy consumption, and minimal area, obviously addressing the real-time constraints. This work aims to face these problems at the middleware level.We show that adaptations in the platform architecture, for instance exploring hardware implementations of middleware services, such as task scheduling and communication, can drive better gains in application requirements like energy and performance, which are essential for embedded applications. This approach is coupled with a high flexibility in choosing either a hardware or a software implementation, because services are encapsulated into objects and the application development and the design space exploration at middleware level can be performed independently from each other, in a fully transparent way. Furthermore, the use of the object-oriented approach reduces time-to-market and development costs.

Hardware-Efficient VLSI Design for Cascade Support Vector Machine with On-Chip Training and Classification Capability

Local processing of machine learning algorithms like support vector machine (SVM) is preferred over the cloud for many real-time embedded applications. However, such embedded systems often have stringent energy constraints besides throughput and accuracy requirements. Hence, hardware-efficient design to compute SVM is critical to enable these applications. In this paper, a hardware-efficient SVM learning unit is proposed using reduced number of multiplications and approximate computing techniques. These design techniques helped the learning unit to achieve 46.97% and 35.72% reductions in area and power when compared with those of the design using full multipliers. The proposed SVM learning unit supports on-chip training and classification. Energy-efficient dual-core, quad-core and octa-core cascade SVM systems were developed using the proposed SVM learning unit to expedite the on-chip training process. The runtime and energy efficiency of the cascade SVM systems improved with an increase in the number of cores. Interestingly, an average speedup of 421x in training time and a remarkable energy reduction of 24,497x were observed for the octa-core cascade SVM system when compared with the software SVM solution running on Intel Core i5-5257U processor. Moreover, the proposed octa-core cascade SVM system showed 73.75% and 65.78% lower area and power, respectively, than those of state-of-the-art cascade SVM architecture.

FPGA Implementations of SVM Classifiers: A Review

Support vector machine (SVM) is a robust machine learning model with high classification accuracy. SVM is widely utilized for online classification in various real-time embedded applications. However, implementing SVM classification algorithm for an embedded system is challenging due to intensive and complicated computations required. Several works attempted to optimize performance and cost by implementing SVM in hardware, especially on field-programmable gate array (FPGA) as it is a promising platform for meeting challenging embedded systems constraints. This article presents a comprehensive survey of hardware architectures used for implementing SVM on FPGA over the period 2010–2019. We performed a critical analysis and comparison of existing works with in-depth discussions around limitations, challenges, and research gaps. We concluded that the primary research gap is overcoming the challenging trade-off between meeting critical embedded systems constraints and achieving efficient and precise classification. Finally, some future research directions are proposed, aiming to address such research gaps.

A Comparative Study of Sorting Algorithms with FPGA Acceleration by High Level Synthesis

Nowadays, sorting is an important operation for several real-time embedded applications. It is one of the most commonly studied problems in computer science. It can be considered as an advantage for some applications such as avionic systems and decision support systems because these applications need asorting algorithm for their implementation. However, sorting a big number of elements and/or real-time decision making need high processing speed. Therefore, accelerating sorting algorithms using FPGA can be an attractive solution. In this paper, we propose an efficient hardware implementation for different sorting algorithms (BubbleSort, InsertionSort, SelectionSort, QuickSort, HeapSort, ShellSort, MergeSort and TimSort) from high-level descriptions in the zynq-7000 platform. In addition, we compare the performance of different algorithms in terms of execution time, standard deviationand resource utilization. From the experimental results, we show that the SelectionSort is 1.01-1.23 times faster than other algorithms when N < 64; Otherwise, TimSortis the best algorithm.

Robust and Large-Scale Convolution through Stochastic-Based Processing without Multipliers

Large-scale discrete convolution, well-known to be computationally intensive, is a fundamental algorithmic building block in many computer vision and artificial intelligence applications. This work presents a novel stochastic-based hardware architecture and design that computes discrete convolution based on the widely-used convolution theorem. Our approach has three advantages. First, it can achieve approximately <inline-formula><tex-math notation="LaTeX">${\mathrm O} (1)$</tex-math></inline-formula> in algorithmic complexity for any given absolute error bound <inline-formula><tex-math notation="LaTeX">$d$</tex-math></inline-formula> and any given input vector size <inline-formula><tex-math notation="LaTeX">$N$</tex-math></inline-formula> . This computing complexity, when compared with <inline-formula><tex-math notation="LaTeX">${\mathrm O} (N^2)$</tex-math></inline-formula> and <inline-formula><tex-math notation="LaTeX">${\mathrm O} (N \log N)$</tex-math></inline-formula> operations for conventional multiplier-based and FFT-based architectures respectively, represents a significant improvement, although at the cost of degraded computing accuracy. Second, to achieve a given computing accuracy, our proposed stochastic-based convolution can be analytically proven to only require a moderate number of random samples, e.g., 788 random samples can achieve 95 percent accuracy at 99 percent confidence level for a convolution with <inline-formula><tex-math notation="LaTeX">$N=128$</tex-math></inline-formula> . Third, this proposed stochastic-based architecture is highly fault-tolerant because the information to be processed is encoded with a large ensemble of random samples. As such, the local perturbations of its computing accuracy will be dissipated globally, thus becoming inconsequential to the final overall results. We believe that, being highly scalable and energy efficient, our stochastic-based convolution architecture is well-suited for many real-time embedded applications, especially those perception-based computing tasks that are inherently fault-tolerant. In short, this work provides an elegant way to tradeoff between computing accuracy and computing performance/hardware efficiency for many real-world convolution-based applications.

A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications

In this brief, we introduce an architecture for accelerating convolution stages in convolutional neural networks (CNNs) implemented in embedded vision systems. The purpose of the architecture is to exploit the inherent parallelism in CNNs to reduce the required bandwidth, resource usage, and power consumption of highly computationally complex convolution operations as required by real-time embedded applications. We also implement the proposed architecture using fixed-point arithmetic on a ZC706 evaluation board that features a Xilinx Zynq-7000 system on-chip, where the embedded ARM processor with high clocking speed is used as the main controller to increase the flexibility and speed. The proposed architecture runs under a frequency of 150 MHz, which leads to 19.2 Giga multiply accumulation operations per second while consuming less than 10 W in power. This is done using only 391 DSP48 modules, which shows significant utilization improvement compared to the state-of-the-art architectures.

Hardware Architecture to Extract Feature Points for Object Recognition

The object recognition is applied to mobile devices and home appliances recently. Accordingly, The SIFT algorithm draws attention for feature point extraction. However, since its process needs excessive amount of computations and memory accesses, SIFT is not a suitable algorithm to implement in software for real-time embedded applications. To solve this problem, we propose a method to implement the SIFT algorithm efficiently. The method changes the computation order to preferentially compute the pixel values required to filter the input image. The second step is that FIFO buffers are used to save next computation images in advance and parallelism is achieved to concurrently perform filtering the images with all Gaussian filters that have different variance values. Finally, the method concurrently subtracts these generated Gaussian images. As a result, this hardware can extract feature points on qVGA(320x240) image in real-time. The proposed hardware is implemented with the Virtex4-LX60 FPGA and the performance is 111fps at 206MHz.

Experimental Evaluation and Selection of Data Consistency Mechanisms for Hard Real-Time Applications on Multicore Platforms

Multicore platforms are increasingly used in real-time embedded applications. In control systems, including automotive, avionics, and automation, resources shared by tasks on different cores need to be protected by mechanisms that guarantee access in a mutually exclusive way with bounded worst case blocking time. The evaluation of the tradeoffs among the possible protocols for mutual exclusion requires an estimate of their implementation overheads. In this paper, we summarize the possible protection mechanisms and provide code implementations in real-time operating systems executing on a multicore platform. We discuss the tradeoffs among the different mechanisms based on experimental evaluation of their memory and timing overheads as well as their impact on system schedulability. We propose a heuristic algorithm to select the optimal combination of mechanisms for shared resources in systems with time constraints to minimize their memory requirements. The effectiveness of the optimization procedure is demonstrated by synthetic systems as well as industrial case studies.

Multiple-Model Linear Kalman Filter Framework for Unpredictable Signals

This paper presents sensor fusion techniques for systems where the process model is a function of the human input and, therefore, unpredictable. The system consists of free and user-driven motion regimes. The free regime can be modeled as a damped sinusoidal waveform, while the driven regime and the transitions between regimes do not respect any sort of probability, pattern, or sequence. The quantity of interest is the deflection of a clamped beam, measured using three sensor technologies: 1) strain gages; 2) infrared; and 3) Hall effect sensors. Experiments using infrared-based motion capture as reference measuring system show that: 1) none of the sensors present optimal performance for both motion regimes and 2) measurement errors of each sensor differ significantly according to the motion regime. These findings suggest the use of sensor fusion techniques with low processing cost, compatible with real-time embedded applications. Our solution is based on a multiple-model linear Kalman filter in combination with motion segmentation. The motion segmentation discriminates gestures according to the knowledge of their process model. This allows a more predictive estimation during periods of free motion, while relying on a less predictive approach for unknown user-driven signals. In addition, we propose a framework on evaluation and selection of process models for unpredictable signals. The implementation was compared with single-sensor and single-model filter designs. Results based on human subject data reveal that the proposed method improves the error covariance of the estimate by a factor of 2.2 for driven motions and 12.7 for free motions in comparison with single-sensor filter design.

A new auto-switched chaotic system and its FPGA implementation

This paper presents a 3D chaotic system which is constructed by an auto-switched numerical resolution of multiple three dimensional continuous chaotic systems. The designed chaotic system provides complex chaotic attractors and can change its behaviors automatically via a chaotic switching-rule. Some complex dynamical behaviors are investigated and analyzed. The originality of the proposed architecture is that allows to solve the problem of the finite precision due to the digital implementation while provides a good trade-off between high security, performance and hardware resources (low power and cost). Hardware digital implementation and FPGA circuit experimental results demonstrate a promising technique can be applied in efficient embedded ciphering communication systems. Moreover, the proposed chaotic system should be very useful for the consideration of reducing negative influence of dynamical degradation in real-time embedded applications.

A Real-Time Flash Memory Storage System in Embedded Environment

Recently, flash memory is becoming a popular data storage device in most of the electronic consumer devices. It has lots of attractive features such as small size and light weight nature, zero noise, solid-state reliability, low power consumption, and better shock resistant. To make it suitable for real-time embedded applications, this paper presents the design of an object based file system that uses parallel operations to guarantee bounded read-write access latencies to real-time tasks, in the presence of requests from non real-time tasks. The proposed scheme requires minimal support from the underlying operating system.

Performance Optimization of the Fuzzy Rule Interpolation Method “FIVE”

Fuzzy Rule Interpolation (FRI) methods are efficient structures for knowledge-representation with relatively few rules. In spite of their good knowledge representation efficiency, their high computational demand makes the FRI methods hardly suitable for embedded real-time applications, for which short reasoning time has a high importance. On the other hand, the fact that currently available devices have increased computational power gives the FRI methods an opportunity to appear in real-time embedded applications. Therefore, the need for a low-computation and lowresource-demand FRI method is emerging. The goal of this paper is to introduce some implementation details of such an FRI method, together with its brief time and space complexity analysis. The paper also gives some hints for further performance optimization possibilities.

Model-driven software synthesis for hard real-time applications with energy constraints

Model-driven methods have been quite effective for reducing the intricacies of embedded software development, since they provide effective means for property verification as well as automatic code generation. Nevertheless, regarding energy-constrained hard real-time systems, few model-driven methods are available and, usually, most methods (model-driven or not) consider simplified system specifications, such as absence of intertask relations. This paper presents a model-driven method for software synthesis of hard real-time embedded applications with energy constraints. A formal model based on time Petri nets is adopted in order to provide a basis for pre-runtime schedule generation and property analysis/verification.

Performance evaluation of intel's quad core processors for embedded applications

Recently, multiprocessing is implemented using either chip multiprocessing (CMP) or Simultaneous multithreading (SMT). Multi-core processors, represent CMP processors, are widely used in desktop and server applications and are now appearing in real-time embedded applications. We are investigating optimal configurations of some of the available multi-core processors suitable for developing real-time software for a multithreaded application used for pavement performance measurements. For the application discussed in this paper we are considering the use of either the Intel core 2 quad or the core i7 (a quad core processor with hyper threading (HT) technology.) Processor performance is a major requirement in this set of real-time, computational intensive embedded applications. The performance of both processors is measured and evaluated using single and multithreaded workloads supplied by different benchmark suites. As for the core i7 processor we also provide an evaluation for the HT technology implemented in each core of this processor.

Reconfigurable system for real-time embedded control applications

This paper discusses the development of embedded controllers on a reconfigurable multiprocessor system using field programmable gate array (FPGA) technology. The system is reconfigurable in hardware and software in the sense that certain components may be reused in different applications, hence allowing rapid development of embedded control systems. Concurrent real-time operation can be achieved by utilising hardware and software modules consisting of dedicated hardware cores and real-time operating systems. For demonstration purposes, we discuss the development of a system consisting of a network-enabled master processor that handles two slave processors each controlling a mechatronic system. The user interface is implemented using an internet browser through the master processor which allows monitoring and supervisory control of the individual systems. A multi-threaded real-time operating system runs on each of the softcore processors which allows flexibility and modularity in software design whereas pre-designed hardware modules on the FPGA chip can be utilised for building comuting hardware for control applications. Experimental results are presented for illustrating how control applications can be developed and deployed using modular components and the hardware/software environment.

Worst-Case Flit and Packet Delay Bounds in Wormhole Networks on Chip

We investigate per-flow flit and packet worst-case delay bounds in on-chip wormhole networks. Such investigation is essential in order to provide guarantees under worst-case conditions in cost-constrained systems, as required by many hard real-time embedded applications. We first propose analysis models for flow control, link and buffer sharing. Based on these analysis models, we obtain an open-ended service analysis model capturing the combined effect of flow control, link and buffer sharing. With the service analysis model, we compute equivalent service curves for individual flows, and then derive their flit and packet delay bounds. Our experimental results verify that our analytical bounds are correct and tight.

Synchronization through Communication in a Massively Parallel Processor Array

Programming MPPAs for complex real-time embedded applications is difficult with conventional multiprogramming models, which usually treat communication and synchronization separately. Based on a programming model for massively parallel embedded computing that is reasonable and productive for software developers, we developed a scalable MPPA chip architecture that delivers tera-ops performance with very good energy efficiency in an ordinary 130-nm ASIC. This MPPA's architecture is based on the structural object programming model, which composes strictly encapsulated processing and memory objects in a structure of self-synchronizing channels. Small RISC CPUs and memories execute the objects.

Synchronization through Communication in a Massively Parallel Processor Array

Programming MPPAs for complex real-time embedded applications is difficult with conventional multiprogramming models, which usually treat communication and synchronization separately. To ease this ...

A general framework for certifying garbage collectors and their mutators

Garbage-collected languages such as Java and C# are becoming more and more widely used in both high-end software and real-time embedded applications. The correctness of the GC implementation is essential to the reliability and security of a large portion of the world's mission-critical software. Unfortunately, garbage collectors--especially incremental and concurrent ones--are extremely hard to implement correctly. In this paper, we present a new uniform approach to verifying the safety of both a mutator and its garbage collector in Hoare-style logic. We define a formal garbage collector interface general enough to reason about a variety of algorithms while allowing the mutator to ignore implementation-specific details of the collector. Our approach supports collectors that require read and write barriers. We have used our approach to mechanically verify assembly implementations of mark-sweep, copying and incremental copying GCs in Coq, as well as sample mutator programs that can be linked with any of the GCs to produce a fully-verified garbage-collected program. Our work provides a foundation for reasoning about complex mutator-collector interaction and makes an important advance toward building fully certified production-quality GCs.