Hardware-Efficient VLSI Design for Cascade Support Vector Machine with On-Chip Training and Classification Capability

Abstract

Local processing of machine learning algorithms like support vector machine (SVM) is preferred over the cloud for many real-time embedded applications. However, such embedded systems often have stringent energy constraints besides throughput and accuracy requirements. Hence, hardware-efficient design to compute SVM is critical to enable these applications. In this paper, a hardware-efficient SVM learning unit is proposed using reduced number of multiplications and approximate computing techniques. These design techniques helped the learning unit to achieve 46.97% and 35.72% reductions in area and power when compared with those of the design using full multipliers. The proposed SVM learning unit supports on-chip training and classification. Energy-efficient dual-core, quad-core and octa-core cascade SVM systems were developed using the proposed SVM learning unit to expedite the on-chip training process. The runtime and energy efficiency of the cascade SVM systems improved with an increase in the number of cores. Interestingly, an average speedup of 421x in training time and a remarkable energy reduction of 24,497x were observed for the octa-core cascade SVM system when compared with the software SVM solution running on Intel Core i5-5257U processor. Moreover, the proposed octa-core cascade SVM system showed 73.75% and 65.78% lower area and power, respectively, than those of state-of-the-art cascade SVM architecture.