Read Delay Research Articles

Design and Analysis of an Ultra-Dense, Low-Leakage, and Fast FeFET-Based Random Access Memory Array

High static power associated with static random access memory (SRAM) represents a bottleneck in increasing the amount of on-chip memory. Novel, emerging nonvolatile memories such as spin-transfer torque magnetic random access memory (STT-RAM), resistive random access memory (RRAM), and ferroelectric field effect transistor-based random access memory (FeFET-RAM) are alternatives for replacing hardware kernels such as SRAM-based last level caches (LLC) due to their fast access times and lower leakage. In this paper, we study an ultra-dense FeFET-RAM based on 1-FeFET memory cells, and address potential disturbance issues at the array level. Disturbances are studied experimentally and via simulation. Experimental measurements are well correlated with modeling results suggesting that we have a good understanding of how disturbance issues will manifest themselves. That said, previous WRITE schemes for 1-FeFET arrays may: 1) exacerbate disturbances and 2) significantly degrade figures of merit (FoM) such as WRITE power. To address these issues, we propose the use of columnwise body connections to simultaneously overcome disturbances and reduce leakage currents during WRITES. We present detailed studies on how 1-FeFET memory cells and arrays (with columnwise body bias) fare when compared to traditional SRAM approaches and other emerging technologies. Notably, we benchmark the 1-FeFET memory against 1T * 1FeFET and 2T * 1FeFET designs proposed in early works, as well as SRAM, STT-RAM, and RRAM. Our evaluation of a $64\times 64$ FeFET-RAM array shows that the area, READ delay, and static power are reduced by $\sim 5.3\times $ , $\sim 1.5\times $ , and $\sim 74\times $ , respectively, when compared to an SRAM equivalent. Also, the 1-FeFET memory cell design shows $\sim 50\times $ improvements in terms of WRITE energy with respect to STT-RAM and RRAM counterparts.

Characterization of Half-Select Free Write Assist 9T SRAM Cell

Modern biomedical applications have created a high demand for low power static random access memory (SRAM). In this article, a reliable low power half-select free-write assist 9T (HFWA9T) cell has been proposed. To analyze the impact of process variations on different design metrics, the proposed cell has been compared with other contemporary designs such as feedback-cutting 7T (7T), fully differential 8T (FD8T), and single-ended disturb free 9T (SEDF9T) cells. The HFWA9T cell exhibits 2.87×/3.37× higher read stability or read static noise margin (RSNM) than that of 7T/FD8T and 1.40×/6.55× higher write ability or write static noise margin (WSNM) than that of FD8T/SEDF9T,2.90×/2.67× and 1.06×/1.01×/5.05× narrower spread in RSNM and WSNM than that of 7T/FD8T and 7T/FD8T/ SEDF9T cells, respectively. In addition, it shows 1.11×/1.03× narrower spread in read delay (TRA) than that of FD8T/SEDF9T and 1.33× shorter TRA than that of SEDF9T cell. Furthermore, it consumes only 0.67×/0.31×/0.48× of the write power and 0.262×/0.605×/0.90× of the read power, respectively, consumed by 7T/FD8T/SEDF9T, while consuming 0.34×/0.96× of static power consumed by 7T/FD8T cell. For all these improvements, it incurs a penalty of 1.62×/1.78× in write delay (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WA</sub> ) compared to 7T/SEDF9T and 1.58×/1.58× in T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RA</sub> compared to 7T/FD8T cell at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 700 mV.

TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages

To mitigate the ever-worsening “power wall” problem, more and more applications need to expand their working voltage to the wide-voltage range including the nearthreshold region. However, the read delay distribution of the static random access memory (SRAM) cells under the nearthreshold voltage shows a more serious long-tail characteristic than that under the nominal voltage due to the process fluctuation. Such degradation of SRAM delay makes the SRAM-based cache a performance bottleneck of systems as well. To avoid unreliable data reading, circuit-level studies use larger/more transistors in a bitcell by sacrificing chip area and the static power of cache arrays. Architectural studies propose the auxiliary error correction or block disabling/remapping methods in fault-tolerant caches, which worsen both the hit latency and energy efficiency due to the complex accessing logic. This article proposes a timing-speculation (TS) cache to boost the cache frequency and improve energy efficiency under low supply voltages. In the TS cache, the voltage differences of bitlines (BLs) are continuously evaluated twice by a sense amplifier (SA), and the access timing error can be detected much earlier than that in prior methods. According to the measurement results from the fabricated chips, the TS L1 cache aggressively increases its frequency to 1.62× and 1.92× compared with the conventional scheme at 0.5- and 0.6-V supply voltages, respectively.

Design of memristor based low power and highly reliable ReRAM cell

A CNFET-based nonvolatile 4CNFET2M resistive RAM (ReRAM) cell is proposed in this paper. In this design, four CNFETs are employed as high-speed, low power and high endurance switches while the two memristors constitute the memory element. In this paper, the proposed 4CNFET2M ReRAM has been compared with the standard 6T SRAM (S6T) cell and the contemporary 2T2M ReRAM cell. The proposed cell shows 1.68 ×/2.14 × shorter read delay (TRA) when compared to S6T/2T2M while exhibiting 4.16 × shorter write delay (TWA) than that of 2T2M @ VDD = 1 V. Moreover, at VDD = 1 V, it displays a 2.32 × narrower spread in TWA than 2T2M as well as 8.0 ×/7.25 × narrower spread in TRA than that of S6T/2T2M. The proposed cell consumes 2.57 × 106 ×/2.70 × lower hold power (HPWR) than that of S6T/2T2M at VDD = 1 V. In addition, it exhibits tolerance to variations in temperature as well as pitch and Vth of memristor. All this is achieved at a 32.44 × penalty in TWA when compared to S6T. The use of CNFET devices, which possess far superior electrical characteristics in comparison to traditional CMOS devices, integrated with memristor technology, paves the way for such major improvements in design metrics of the proposed cell.

PERANCANGAN SISTEM MONITORING SUHU DAN KADAR AIR PAKAN IKAN PADA PURWARUPA PENGERING PAKAN IKAN MENGGUNAKAN VISUAL STUDIO

Fish feed dryer in the FPIK Lab (Faculty of Fisheries and Marine Sciences) Diponegoro University still uses manual monitoring so it is less effective. Therefore, a good monitoring is needed to deal with problems in the fish feed dryer in the FPIK UNDIP Lab. In this Final Project designed a temperature and water content monitoring system using LCD and Visual Studio applications. In this Final Project there are 3 tests including LCD testing, Visual Studio form, and alarm testing. The results of monitoring the temperature data and water content of fish feed on the prototype of fish feed dryer through LCD and Visual Studio form successfully went well with the reading delay through Visual Studio by 1 second. Ready feed alarm testing has been successfully carried out when humidity reaches 10% RH and moisture content is 10%. Overheat alarm testing has been performed when the temperature reaches 5 ° C above the given setpoint for 10 seconds. And the below setpoint test was successful when the temperature did not reach the setpoint in the range of 5 ° C below the given setpoint.

Read‐decoupled 8T1R non‐volatile SRAM with dual‐mode option and high restore yield

This Letter proposes a read-decoupled (RD) and average 8T1R non-volatile static RAM (SRAM), RD-8T1R. It uses only one memristor to achieve 2 × store energy reduction and higher restore yield compared with other two memristors based non-volatile SRAMs. In addition, this structure can offer two alternative SRAM modes unlike previously known non-volatile SRAMs, i.e. a high speed and a stable mode. Compared with existing technologies, the simulation results in TSMC-65 nm show that the proposed scheme provides a remarkable restore yield. There are ∼ 154% improvement in the read static noise margin (@typical–typical (@TT) corner and stable mode) and ∼ 23% improvement in the read delay (@TT corner and high speed mode) compared with the previous 6T/7T/8 T non-volatile SRAMs.

Are changes in the stomatognatic system able to modify the eye balance in dyslexia?

ObjectivesTo clarify the link between eye muscle function and oral information by comparing 21 dyslexic readers (DR) and 14 normal readers (NR). MethodsChanges in vertical heterophoria (VH) were measured using the Maddox Rod Test performed according to oral modifications and postural conditions. The Spearman correlation was used to assess whether reading delay was correlated with the lability index. ResultsOverall, 50% of NR children and 81% of DR experienced at least one variation in visual perception (p = 0.053). Among DR, the less reading delay they had, the higher their index of lability (p = 0.026), whereas there was no significant correlation among NR. Changes in the Maddox Test were more frequent in DR than in NR after the addition of sensory and postural stimuli, except for one specific posture. For sensory stimuli, the mean lability index was 1.35 in NR and 4.19 in DR, (p = 0.001). For postural stimuli, it was 0.71 and 2.61, (p = 0.003). ConclusionsIt is possible to modify visual perception by changing sensory or mechanical stimuli. Changes are more frequent in DR than in NR. Postural control can be improved with guided oral stimulations. SignificanceThese results reinforce the importance of professional cooperation in the care of dyslexic readers.

Design of CNFET based power- and variability-aware nonvolatile RRAM cell

In this paper a Power– and Variability–Aware Nonvolatile RRAM Cell (4CNFET2M) is presented. Memristor is used as a nonvolatile memory element. We have compared our proposed cell with standard 6T SRAM (S6T) cell and 2T2M RRAM cell (state of the art design based on memristor). The proposed cell shows 1.26 × /3.61 × shorter read delay/write delay variability compared to 2T2M. 4CNFET2M also shows 1.39 × narrower read delay variability compared to S6T. Furthermore, the proposed cell shows 6.4 × shorter write delay in comparison to 2T2M RRAM cell. 4CNFET2M consumes 106 × /2.02 × lower power during hold mode compared to conventional S6T SRAM/2T2M RRAM cell. Furthermore, the proposed cell also shows improvement in hold power variability compared to both the cells. All the simulated data, presented here, are for 1 V supply voltage. These improvements are achieved because of using the memristor and CNFET technology. These benefits are obtained at a cost of slightly longer read delay compared to 2T2M/S6T and 33.6 × longer write delay compared to S6T.

The profile of very preterm children on academic achievement. A cross-population comparison with children with specific learning disorders

BackgroundVery preterm (VPT) children showed delays in reading, spelling and maths, but their academic achievement profile is not clearly understood. AimsVPT children were compared with children with specific learning disorders (SLD) and typically developing (TD) children on academic achievement, considering cognitive and linguistic phenotypic markers. A learning profile analysis was also performed. MethodsWe included 170 10-year old monolingual Italian-speaking children (37 VPT, 28 SLD, 105 TD) assessing cognitive, linguistic and academic skills. ResultsOn academic achievements VPT children fell behind TD peers in some reading (text speed, comprehension), spelling (non-word), and math (number knowledge, written calculations and problem-solving) tasks. SLD children underperformed in all academic tasks with respect to VPT and TD peers. Concerning cognitive and linguistic phenotypic markers, compared to TD peers, VPT children showed lower scores in verbal IQ and phonological fluency, SLD children in phonological processing and rapid automatized naming. VPT children showed a higher rate of at-risk performance in reading compared to TD group, but a minor percentage of impaired profiles and comorbidity among learning areas compared to SLD group. Conclusions and implicationsThe academic achievement profile of VPT children shows persistent delays, but it differs to that of SLD children, since delays are less widespread and severe, and differences were found in phenotypic markers and comorbidity. Follow-up programs and effective interventions are needed for VPT children.

Delays in the reading and spelling of children with cerebral palsy: Associations with phonological and visual processes

BackgroundThis investigation addresses the question of whether there exists a significant discrepancy in the cognitive abilities of children with cerebral palsy (CP) who, despite the presence of age appropriate communication and language, have reading and spelling delays. AimsWe wanted to discover whether there was a relationship between the phonological and visual perceptual abilities of children with CP and their progress in reading and spelling. Methods and proceduresFifteen children with CP (aged between 6:9 years and 11:6 years) were assessed on reading and spelling; communication and language; non-verbal reasoning; phonological processing; and visual perception. Outcomes and resultsTen of the children had very weak reading and spelling skills. Five children had (mostly) age appropriate scores of reading and spelling. No differences were found between these two groups in non-verbal reasoning or communication and language. However, phonological abilities, visual sequential memory and perception of visuospatial relationships were found to be related to reading and spelling. Conclusions and implicationsThe findings suggest that children with CP are at risk for reading and spelling delays when they have poor phonological processing, visual sequential memory and perception of visuospatial relationships. The implications of the findings for classroom practice are discussed.

Microstructural properties of white matter pathways in relation tosubsequent reading abilities in children: a longitudinal analysis.

Microstructural properties of white matter pathways are associated with concurrent reading abilities in children. In this longitudinal study, we asked whether properties of white matter pathways at the onset of learning to read would be associated with reading abilities at older ages. Children (N = 37) with a wide range of reading abilities completed standardized measures of language and phonological awareness and diffusion MRI at age 6years. Mean tract-fractional anisotropy (FA) was extracted from reading-related pathways. At age 8, the same children were re-assessed using a standardized reading measure. Using linear regressions, we examined the contribution of tract-FA at age 6 to reading outcome at age 8, beyond known demographic and pre-literacy predictors of reading. Tract-FA of the left arcuate, left and right superior longitudinal fasciculus (SLF), and left inferior cerebellar peduncle (ICP) made unique contributions to reading outcome after consideration of sex and family history of reading delays. Tract-FA of the left and right SLF and left ICP made unique contributions to reading outcome after the addition of pre-literacy skills. Thus, cerebellar and bilateral cortical pathways represented a network associated with subsequent reading abilities. Early white matter properties may be associated with other neuropsychological functions that predict reading or may influence reading development, independent of reading-related abilities. Tract FA at early stages of learning to read may serve as a biomarker of later reading abilities.

Characterization of a novel 10T SRAM cell with improved data stability and delay performance for 20-nm tri-gated FinFET technology

PurposeThis paper aims to propose a new ten-transistor (10T) SRAM bit-cell with differential read and write operations. The cell structure has read buffer on each side of the cell to improve read performance and comprises six main body transistors’ connections similar to the commercial 6T SRAM cell to improve write performance. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on a silicon-on-insulator (SOI) substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell. The proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher read static noise margin (RSNM) as compared with that of 8T and 6T bit-cells, respectively, at a VDD of 0.9 V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit- cell. The overall electrical quality of the SRAM circuit with the proposed bit-cell is enhanced up to 1.673 times and 1.22 times as compared with the 8T SRAM-NEW and 6T bit-cells, respectively.Design/methodology/approachA new 10T SRAM bit-cell with differential read and write operations is proposed. The proposed bit-cell is designed with tri-gated FinFET technology and implemented on an SOI substrate. 3D TCAD simulations are performed to characterize the efficacy of the proposed bit-cell. Performance characteristics of the proposed bit-cell are compared with the recently reported 8T bit-cell as well as the commercial 6T cell.FindingsThe proposed bit-cell achieves 26.50 per cent and 35.10 per cent higher RSNM as compared with that of the 8T and 6T bit-cells, respectively, at a VDD of 0.9V. The proposed bit-cell also offers 54.78 per cent and 21.18 per cent smaller read delay compared with the 8T SRAM-NEW and 6T bit-cells, respectively. The static power dissipation of the proposed bit-cell is comparable with that of the 6T bit-cell and 24.5 per cent lesser compared with that of the 8T bit-cell.Originality/valueThe proposed bit-cell is novel compared with existing bit-cells.

Clinical and Electrophysiological Differences between Subjects with Dysphonetic Dyslexia and Non-Specific Reading Delay.

Reading is essentially a two-channel function, requiring the integration of intact visual and auditory processes both peripheral and central. It is essential for normal reading that these component processes go forward automatically. Based on this model, Boder described three main subtypes of dyslexia: dysphonetic dyslexia (DD), dyseidetic, mixed and besides a fourth group defined non-specific reading delay (NSRD). The subtypes are identified by an algorithm that considers the reading quotient and the % of errors in the spelling test. Chiarenza and Bindelli have developed the Direct Test of Reading and Spelling (DTRS), a computerized, modified and validated version to the Italian language of the Boder test. The sample consisted of 169 subjects with DD and 36 children with NSRD. The diagnosis of dyslexia was made according to the DSM-V criteria. The DTRS was used to identify the dyslexia subtypes and the NSRD group. 2–5 min of artefact-free EEG (electroencephalogram), recorded at rest with eyes closed, according to 10–20 system were analyzed. Stability based Biomarkers identification methodology was applied to the DTRS and the quantitative EEG (QEEG). The reading quotients and the errors of the reading and spelling test were significantly different in the two groups. The DD group had significantly higher activity in delta and theta bands compared to NSRD group in the frontal, central and parietal areas bilaterally. The classification equation for the QEEG, both at the scalp and the sources levels, obtained an area under the robust Receiver Operating Curve (ROC) of 0.73. However, we obtained a discrimination equation for the DTRS items which did not participate in the Boder classification algorithm, with a specificity and sensitivity of 0.94 to discriminate DD from NSRD. These results demonstrate for the first time the existence of different neuropsychological and neurophysiological patterns between children with DD and children with NSRD. They may also provide clinicians and therapists warning signals deriving from the anamnesis and the results of the DTRS that should lead to an earlier diagnosis of reading delay, which is usually very late diagnosed and therefore, untreated until the secondary school level.

Reading in Children With Fragile X Syndrome: Phonological Awareness and Feasibility of Intervention.

Individuals with fragile X syndrome (FXS) present with significant deficits in reading skills, but scant research exists to understand the characteristics of the reading delays or best practices for reading instruction with this population. Study 1 examined the relationship between phonological awareness and reading skills in individuals with FXS. Study 2 evaluated the feasibility of a web-based reading intervention, which incorporated phonological awareness and phonics instruction but was originally developed for mainstream students, for children with FXS. Results suggest that phonological awareness and reading skills are correlated in this population, and that instruction targeting phonological awareness and phonics should not be ruled out for individuals with FXS. Further studies are needed to examine their potential effects.

Achievement attributions are associated with specific rather than general learning delays

The causal attributions that children make for success and failure have been associated with later reading motivation and ability perceptions, which have the potential to impact future task engagement. Few studies have investigated whether such attributions are domain specific, that is linked with the specific skill in question, or a general motivational set. Even fewer studies have examined these relationships among diverse racial and ethnic subgroups. The present study examined differences in success and failure attributions among children with and without reading delay (RD) and general language impairments (LI), in a predominately Hispanic and African American sample. Participants were 1311 children, 8 to 15 years old. Significant differences in ability attributions were observed between participants with and without RD and LI, with no additive effect for cases with co-occurring reading and language impairments. When reading and vocabulary were evaluated continuously, significant and substantial positive relationships were observed between skill and ability attributions in situations of success, and negative associations observed in situations of failure. Weaker relationships were observed for vocabulary, though vocabulary did function as a moderator in the relationship between reading skill and ability attributions, with stronger associations at higher vocabulary levels. Overall, the findings suggest that ability attributions for reading success and failure are linked with reading skill and/or deficits, and not with general language impairments.

Infância na casa de acolhimento no contexto prisional: um olhar sobre o crescimento e desenvolvimento

Objetivo: Avaliar o crescimento e desenvolvimento nos aspectos, psicomotores e cognitivos nas crianças filhas de mães em situação de prisão que vivem em uma creche. Método: Estudo de campo de caráter descritivo e abordagem qualitativa. Participaram da pesquisa 09 crianças da casa de acolhimento Nova Semente, extensão do complexo Penitenciário Lemos de Brito alocado na cidade de Salvador – BA no mês de maio de 2016. Resultados: Entre as crianças, 54,6% eram do sexo feminino e 63,6% estavam na faixa etária entre 24 a 72 meses. Percebeu-se que todas as crianças apresentaram estatura adequada para a idade. Assim como, 100% apresentaram percentil nutricional dentro da normalidade. Algumas crianças encontravam-se com o desenvolvimento afetado, revelado pelo atraso na leitura, contagem de numerais, identificação de cores, além do atraso social. Conclusão: Esses resultados mostram a necessidade da atuação da equipe multidisciplinar que assistem essas crianças para promoverem estratégias que aprimorem a assistência frente o seu desenvolvimento.

Optimization of instrument conditions for the analysis for mercury, arsenic, antimony and selenium by atomic absorption spectroscopy

The chemical vapor generation atomic absorption spectrometry technique is extremely popular for trace analysis specifically hydride generation continuous flow systems for arsenic, antimony, selenium and cold vapor for mercury. Optimizing the instrument parameters as well as the hydride generating reactions will improve the sensitivity and reliability of the results obtained. The advantage of optimizing these conditions increases the production of hydrides or vapor species formed thereby improving recoveries. In addition this helps to reduce chemical interferences from other species that may compete with the analyte of interest for hydride formation. Parameters optimized include:•Reagent flow rate•Sample flow rate•Argon flow rate•Acetylene/Air ratio•Concentration of reagents•Read delay timeFor the analytical procedure the flow rate of the reagents and sample was affected by the tension on the peristaltic pump and the size of the tubing. The optimized flow rate for all reagents was between 0.9–1.0?mL/min and between 6–7?mL/min for the sample when both conditions were applied. The optimized type and concentrations of the reducing agent for Arsenic, Antimony and Selenium were NaBH4 (0.6% w/v), NaBH4 (0.7% w/v) and NaBH4 (0.1% w/v) in NaOH (0.5% w/v) respectively and SnCl2 (25% w/v) in HCl (20% v/v) for Mercury. The concentration and type of acid that produced the optimum signals for Arsenic, Antimony and Selenium were 5, 10 and 10?mol/dm-3 respectively. The flow rates for the carrier gas (Argon) for Arsenic, Antimony, Selenium and Mercury were optimized at 0.2, 0.2, 2.0 and 2.0?mL/min respectively. The optimized flow rate for fuel gas (Acetylene) for all the metals except Mercury was 2.5?mL/min. The optimized Instrument Read Delay Time for Mercury was 70?s and 20?s for Arsenic, Antimony and Selenium.

Evaluation of the Effect of Light and Scanning Time Delay on The Image Quality of Intra Oral Photostimulable Phosphor Plates.

Background:Nowadays, digital radiography is widely used in dental practice. One of the most common types is Photo Stimulated Phosphor Plate (PSP).Objective:The aims of this experimental study were to evaluate the impacts of different combinations of storage conditions and varying delays in reading of digital images captured using PSPs.Methods:Standardized images of a step wedges were obtained using PSPs from the Digora digital systems. Plates were exposed and immediately scanned to produce the baseline gold standard. The plates were re-exposed and stored in four different storage conditions: white light, yellow light, natural light environment and dark room, then scanned after 10 and 30 minutes and 4 and 8 hours. Objective analysis was conducted by density measurements and the data were analyzed statistically using GEE test. Subjective analysis was performed by two oral and maxillofacial radiologists and the results were analyzed using McNemar’s test.Results:The results from GEE analysis show that in the natural light environment, the densities in 10 minutes did not differ from the baseline. The mean densities decreased significantly during the time in all environments. The mean densities in step 2 for the dark room environment decreased with a slighter slope in comparison to yellow environment significantly.Conclusion:PSP images showed significant decrease in the density in plates scanned for 10 minutes or longer after exposure which may not be detected clinically. The yellow light environment had a different impact on the quality of PSP images. The spatial resolution did not change significantly with time.

Computer-assisted language learning in reading comprehension by using visual mnemonics A case study of Iranian EFL learners

A profitable method to address reading delays is to use computer-assisted learning, but these techniques are not always effective. In this research, the researchers evaluated a commercially available computer system, which uses visual mnemonics, in a randomised controlled trial with 78 English-speaking children (mean age 7 years) who their schools identified as needing reading support. School based individual tutorials usually took place 2-3 times/week. Only the experimental group received the intervention in the first 10 months, thereafter both the experimental and control groups received the intervention for 6 months. After 10 months, the experimental group had significantly higher standardised scores than the waiting list control group of decoding, phonological awareness, naming speed, phonological short-term memory and executive loaded working memory. The computer-assisted intervention was effective and this suggests that this medium can be used for reading interventions with English speaking children.

A near-threshold 10T differential SRAM cell with high read and write margins for tri-gated FinFET technology

In this paper, a new 10T SRAM bit-cell working in the near-threshold region with differential read and write operations is proposed. The cell structure comprises six main body transistors having connections similar to commercial 6T SRAM cell to improve write performance and has a separate read buffer on each side of cell to improve read performance. Efficacy of the proposed bit-cell is tested in 20nm tri-gated FinFET technology with the help of HSPICE simulations in near-VT and super-VT operating regions. Performance characteristics of the proposed bit-cell are compared with other recently reported 10T and 8T differential sensing bit-cells, along with the commercial 6T cell. The proposed bit-cell achieves 6.57%, 33.33% and 51.64% higher RSNM as compared to 10T P-P-N, 8T SRAM-NEW and 6T bit-cells, respectively, in near-VT operating region. The read delay, write delay and static power consumption of the proposed bit-cell are comparable with that of 6T bit-cell in both operating regions. The overall electrical quality of SRAM circuit with the proposed bit cell is enhanced up to 8.192, 1.13 and 2.39 times compared to that of the 10T P-P-N, 8T SRAM-NEW and 6T bit-cells, respectively, in near-VT operating region. The proposed bit-cell can operate with a 38.8%, 30% and 5.54% lower VDD as compared with 6T, 8T SRAM-NEW and 10T P-P-N bit-cells, respectively, under equal read data stability conditions. Influence of process variation on bit-cell stability is studied through 10,000 Monte Carlo simulations. The study shows that the proposed bit-cell meets the required six sigma value (6σ) for all operations even at VDD =0.5V. Variations in the bit-cell performance metrics for temperature rise from −40°C to 100°C are also studied.