Read Margin Research Articles

Enhanced Current-voltage Nonlinearity by Controlling Oxygen Concentration of TiO<SUB>x</SUB> Buffer Layer for RRAM Passive Crossbar Array

As a next-generation memory, resistive random access memory (RRAM) is attracting attention for its fast speed and non-volatility. Nevertheless, an additional selecting element is required to solve the sneak path problem. However, nonlinear devices such as transistors and selectors not only degrade density of the RRAM array, but also increase difficulty of 3D integration. Therefore, in this study, we propose a method for improving the current-voltage (I-V) nonlinearity of an Pt/Al₂O₃/TiOSUBx/SUB/Ti/Pt RRAM. Oxygen concentration was controlled based on electrical flexibility of TiOSUBx/SUB encompassing metallic and semiconducting properties; and three devices with different TiOSUBx/SUB were fabricated. As the O/Ti atomic ratio increases from 1.31 to 1.74, the enhanced I-V nonlinearity was confirmed, which was also quantitatively verified through fitting with a hyperbolic sine function. Reflecting the measured nonlinearity, RRAM passive array was constructed and its read margin was investigated by SPICE simulation. As a result, it is demonstrated that the read margin was improved by increasing the nonlinearity. For TiOSUB1.74/SUB sample which exhibits the highest nonlinearity, a read margin of 22.97% was achieved in 2SUP7/SUP × 2SUP7/SUP array size. By increasing the nonlinearity of RRAM devices, it is expected that RRAM passive array can be utilized for future high-density storage class memory.

Dynamical Effects of Excess Carriers on SOI FeFET Memory Device Operations

We study the carrier dynamics of memory program (PGM) and readout operations for an n-type silicon-on-insulator (SOI) ferroelectric field-effect transistor (FeFET) through TCAD simulations. We found that gate-induced drain leakages (GIDL) during the PGM operation with large negative gate biases can result in excess hole concentrations as high as 7.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 10^{{20}}$ </tex-math></inline-formula> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-{3}}$ </tex-math></inline-formula> in the potential well formed in the SOI channel. The hole accumulation causes a large electric field across the ferroelectric (FE) layer and results in a polarization boost at a low PGM voltage. For a nano-scale SOI channel, the retention time of the excess holes can exceed microseconds according to our simulations. The outflow of the excess holes leads to a transient effect in the drain current during the readout operation, and we observed additional retention effects for the FeFET memory window due to the hole dynamic effects on the electrostatics and the FE polarizations. While the excess holes result in a ~100 ps delay in the readout phase before a large read margin can be detected, they have boosted the PGM speed and polarization window. The boosted polarization can be retained for milliseconds, and potentially beyond, resulting in an appreciable ON/OFF ratio during readout. Therefore, such effects can be utilized for low-power memory applications through proper SOI FeFET designs with the awareness of excess carrier dynamics.

VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators

Non-volatile memory (NVM) such as RRAM and PCM has become the key component in high energy efficiency computing-in-memory (CIM) architectures. However, the computing accuracy and energy efficiency improvement of conventional 1T1R RRAM array based current sensing CIM scheme is hindered by device variation and large output current. In this work, we propose a voltage sensing differential column architecture (VSDCA) based on 1T2R RRAM array for binary memory and CIM applications. The memory mode of VSDCA macro can improve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.12\times $ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.29\times $ </tex-math></inline-formula> relative read margin compared to conventional 1T1R current sensing memory. The computing mode supports 8-bit input, 9-bit weight and 18-bit output high precision and rows fully parallel computing. The VSDCA macro design is evaluated under SMIC 40 nm technology node, the energy efficiency for the high precision CIM reaches 39.52 TOPS/W. The CIFAR10 inference accuracy of the simulated VGG16 and ResNet18 model is 85.91% and 89.32% respectively.

Advances in Magnetic Domain Walls and Their Applications

This article explores the recent developments in spin-based domain wall (DW) memories. The physics behind the DW motion, device materials, current challenges, and applications have been discussed in detail. DWs can propagate through a magnetic nanowire by the application of external magnetic fields or by spin-polarized electric currents. Great progress has been made in these devices since the introduction of electric current-induced DW motion. However, driving DWs necessitates large spin-current densities that are incompatible with low-power devices. Therefore, significant efforts have been made to achieve highly efficient and controlled DW motion by material engineering and different mechanisms such as spin-orbit-torque (SOT), Dzyaloshinskii-Moriya interaction (DMI), and voltage-controlled magnetic anisotropy. The controlled manipulation of DWs in magnetic materials has inspired numerous strategies for high-density memory and energy-efficient logic implementation. Moreover, these devices are the potential candidates for neuromorphic computing applications that can be combined with logic-in-memory. The displacement of the DW can achieve multiple resistance states that have opened up possibilities of building artificial neurons and synapses. Despite the rapid progress, DW devices face several challenges such as low read margin, low speed, and sub-20nm scalability. Future research directions have to focus on material engineering and fabrication techniques to address these issues. Simultaneously, efforts from the circuit and system perspectives are extensively required in exploring the possible uses of these devices.

Memristive Switching and Density-Functional Theory Calculations in Double Nitride Insulating Layers.

In this paper, we demonstrate a device using a Ni/SiN/BN/p+-Si structure with improved performance in terms of a good ON/OFF ratio, excellent stability, and low power consumption when compared with single-layer Ni/SiN/p+-Si and Ni/BN/p+-Si devices. Its switching mechanism can be explained by trapping and de-trapping via nitride-related vacancies. We also reveal how higher nonlinearity and rectification ratio in a bilayer device is beneficial for enlarging the read margin in a cross-point array structure. In addition, we conduct a theoretical investigation for the interface charge accumulation/depletion in the SiN/BN layers that are responsible for defect creation at the interface and how this accounts for the improved switching characteristics.

Improved threshold switching characteristics of vanadium oxide/oxynitride-based multilayer selector in a cross-point array

We developed a selector device with the bi-directional threshold switching characteristics of vanadium oxide (VOx) by implementing vanadium oxynitride (VOx:Ny) in a sandwich structure. The proposed device with the Pt/VOx:Ny/VOx/VOx:Ny/Pt structure as opposed to a cell with a Pt/VOx/Pt structure exhibits lower off-current and stable switching characteristics. The elements of the device were analyzed using high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy, and its memory characteristics were verified by applying the Pt/VOx:Ny/VOx/VOx:Ny/Pt selector to amorphous indium-gallium-zinc oxide-based resistive switching (RS) devices in the 1 selector-1 ReRAM structure. Our device shows stable RS properties over 100 DC cycles and> 106 AC cycles, an improved ON/OFF ratio (~67), a high switching speed (<110 ns), and a rectification ratio of ~1 × 103 when the read margin is 10%.

Comparison of 2-D MoS2 and Si Ferroelectric FET Nonvolatile Memories Considering the Trapped-Charge-Induced Variability

This brief investigates scaled 2-D MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) considering the trapped-charge-induced variability with the aid of Technology Computer Aided Design (TCAD) atomistic simulations. Our study indicates that, compared with the Si channel, the monolayer MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> channel with larger electron affinity and bandgap energy can result in an FeFET NVM with larger memory window (MW). Moreover, due to its lower channel permittivity and channel thickness, the 2-D MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FeFET possesses a superior immunity to trapped-charge-induced variability, and the gap in MW between MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and Si FeFETs enlarges under the presence of trapped charges. Besides, due to its atomically thin channel thickness and superior electrostatic integrity, the scaled 2-D MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FeFET possesses a remarkably better read margin than the Si counterpart. Our study may provide insights for future scaling of FeFET NVMs.

A Dual-Domain Dynamic Reference Sensing for Reliable Read Operation in SOT-MRAM

Although spin orbit torque magnetic random access memory (SOT-MRAM) is one of the strong candidates for next-generation embedded memories, the degradation of read margin due to low tunnel magnetoresistance ratio (TMR) with process variations has been a large concern. In this paper, we present the dual-domain dynamic reference (DDDR) sensing scheme, where the reference voltage can be dynamically changed based on the combined voltage and time domain sensing to increase the sensing margin. The Half Schmitt trigger and sample & hold circuits are efficiently employed to generate data-dependent reference voltages and to store the sampled voltage levels at different times, respectively. According to the simulations using 28nm CMOS technology with 128 by 128 SOT-MRAM array, the proposed DDDR approach achieves a 243mV of sensing margin under 6.08E-8 bit-error-rate (BER) at 1.76ns, which is 2X larger margin with more than 100 times lower BER compared to the conventional read scheme. When scaling down the pre-charge voltage, the proposed scheme achieves more than 50% of the read energy savings under 1E-5 target BER condition.

Correlation between resistive switching characteristics and density of traps observed in Zr3N2 resistive switching memory devices with TiN barrier electrode

In this study, we present a correlation between the resistive switching (RS) characteristics and the traps of Zr3N2, which is based resistive random-access memory (RRAM) with a TiN barrier electrode, in order to identify the RS mechanism of the trap-based RRAM devices. First, gradual asymmetrical RS properties were discovered in the RS test, which included a current ratio of >2.51 × 102 and a large read margin of 480. As a result of analyzing the trap, the RS characteristics were deeply related to the nitride trap density (Nnt) in the Zr3N2 films as opposed to the interface trap density (Nit) at Zr3N2/p-Si layer. In addition, in the trap evaluation for four different resistance states, we observed that the Nnt was consistently increased with a decreasing resistance. These results indicate that the resistance state of the proposed TiN/Zr3N2/p-Si memory cell is determined by the Nnt, which means that controlling the Nnt is important in order to achieve a stable resistance state.

A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array

A sneak current compensation scheme with offset cancellation sensing circuit (SCC-OCSC) adopting dummy bitline and wordline is proposed to resolve sneak current problem in the cross-point memory array. The sneak current degrades sensing yield because it disturbs read operation for high resistance cell, especially, by contaminating read current. Since the sneak current increases proportionally to the array size, the array size is limited to achieve the target sensing yield, which makes it hard to implement high density memory. The proposed SCC-OCSC cancels-out the sneak current through two phases. In first phase, the sneak current is sampled by connecting dummy BL or WL to the sensing circuit. In the second phase, the sneak current is compensated by subtracting the current sampled in the first phase. Furthermore, sensing yield is enhanced by applying the offset cancellation technique, sharing the same sensing circuit in the two phases. The proposed SCC-OCSCs with dummy BL and WL effectively improve read margin with generally used biasing schemes, floating and half-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> schemes, respectively. In Monte-carlo simulation including post-layout sensing circuit with 65nm CMOS technology, it is verified that sensing yield is significantly improved. Thus, the array size assigned to single sensing circuit is extended up to 8-times with SCC-OCSC, leading 88% area reduction with reduced number of required sensing circuit. Performance is improved as 66% and 25% while power consumption is improved as 47% and 37%, by SCC-OCSC with dummy BL in floating scheme and SCC-OCSC with dummy WL in half-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> scheme, respectively.

A Nonvolatile 7T2M SRAM Cell with Improved Noise Margin for Energy Efficient In Memory Boolean Computations

The current computing systems are facing von Neumann bottleneck (VNB) in modern times due to the high prominence on big-data applications such as artificial intelligence and neuromorphic computing. In-memory computation is one of the emerging computing paradigms to mitigate this VNB. In this paper, a memristor-based robust 7T2M Nonvolatile-SRAM (NvSRAM) is proposed for energy-efficient In-memory computation. The 7T2M NvSRAM is designed using CMOS and memristor with a higher resistance ratio, which improved the write margin by 74.44% and the energy consumption for read and write operation by 5.10% and 9.66% over conventional 6T SRAM at the cost of increment in write delay. The read decoupled path with the VGND line enhances the read margin and read path Ion/Ioff ratio of 7T2M NvSRAM cell by 2.69× and 102.42%, respectively over conventional 6T SRAM. The proposed cell uses a stacking transistor to reduce the leakage power in standby mode by 64.20% over conventional 6T SRAM. In addition to the normal SRAM function, the proposed 7T2M NvSRAM performs In-Memory Boolean Computation (IMBC) operations such as NAND, AND, NOR, OR, and XOR in a single cycle without compute-disturb (stored data flips during IMC). It achieves 4.29-fJ/bit average energy consumption at 1.8 V for IMBC operations

Effect of the Oxygen Composition Control of HfOx Films on Threshold and Memory Switching Characteristics for Hybrid Memory Applications

AbstractConsidering a high‐density vertical X‐point memory array, the film thickness of an active device for the selector and memory needs to be scaled down. Here, the authors propose an AgTe/HfOx‐based hybrid memory device with a film thickness of less than 10 nm by adopting a bilayer (HfO1.8/HfO2) film using precise composition control. Non‐volatile switching characteristics can be obtained by considering the formation of stable nanoscale Ag filaments in the nanoporous region in non‐stoichiometric HfO1.8 deposited via sputtering. By contrast, volatile switching characteristics are achieved by an unstable atomic‐scale Ag path in stoichiometric HfO2 deposited via plasma‐enhanced atomic layer deposition. Based on density functional theory calculations, it is confirmed that the stoichiometry of the HfOx film is the key parameter that controls the switching characteristics. The bilayer (HfO1.8/HfO2) device exhibits excellent hybrid memory characteristics, such as distinct read margin (&gt;1.5 V), high ON/OFF ratio (&gt;106), and extremely low OFF current (≈pA), for vertical X‐point memory applications.

Improved Resistive Switching Observed in Ti/Zr3N2/p-Si Capacitor via Hydrogen Passivation

Charge-trap based resistive switching (RS) has attracted attention in the resistive random-access memory (RRAM) industry due to its gradual RS behavior for multi-level and synaptic applications. In this work, in order to lower the operating current level closely related to device&#x2019;s degradation, we applied a hydrogen passivation to Zr₃N₂ based RRAM devices and investigated the correlation between current level and trap density, such as an interface trap density (<inline-formula> <tex-math notation="LaTeX">$\text{N}_{\mathrm {it}}$ </tex-math></inline-formula>) at the Zr<inline-formula> <tex-math notation="LaTeX">$_{3}\text{N}_{2}/p$ </tex-math></inline-formula>-Si layer and nitride trap density (<inline-formula> <tex-math notation="LaTeX">$\text{N}_{\mathrm {nt}}$ </tex-math></inline-formula>) within Zr₃N₂ films, for memory cells annealed in conventional N₂ gas as well as H₂ gas. Compared to the N₂-annealed sample, after H₂ annealing, <inline-formula> <tex-math notation="LaTeX">$\text{N}_{\mathrm {it}}$ </tex-math></inline-formula> is lowered by the hydrogen passivation effect, which results in a reduction of both current level at high resistive state (HRS) and variation of HRS and low resistive state (LRS). As a result, in the H₂ annealed Zr₃N₂ RRAM cell, we observed a lower operation voltage/current, longer endurance, and larger read margin due to the hydrogen passivation effect.

Selector-less Ferroelectric Tunnel Junctions by Stress Engineering and an Imprinting Effect for High-Density Cross-Point Synapse Arrays

In the quest for highly scalable and three-dimensional (3D) stackable memory components, ferroelectric tunnel junction (FTJ) crossbar architectures are promising technologies for nonvolatile logic and neuromorphic computing. Most FTJs, however, require additional nonlinear devices to suppress sneak-path current, limiting large-scale arrays in practical applications. Moreover, the giant tunneling electroresistance (TER) remains challenging due to their inherent weak polarization. Here, we present that the employment of a diffusion barrier layer as well as a bottom metal electrode having a significantly low thermal expansion coefficient has been identified as an important way to enhance the strain, stabilize the ferroelectricity, and manage the leakage current in ultrathin hafnia film, achieving a high TER of 100, negligible resistance changes even up to 108 cycles, and a high switching speed of a few tens of nanoseconds. Also, we demonstrate that the usage of an imprinting effect in a ferroelectric capacitor induced by an ionized oxygen vacancy near the electrode results in highly asymmetric current-voltage characteristics with a rectifying ratio of 1000. Notably, the proposed FTJ exhibits a high density array size (>4k) with a securing read margin of 10%. These findings provide a guideline for the design of high-performance and selector-free FTJ devices for large-scale crossbar arrays in neuromorphic applications.

A 9T FinFET SRAM cell for ultra-low power application in the subthreshold regime

Due to the scaling of the CMOS, the limitations of these devices raised the need for alternative nano-devices. Various devices are proposed like FinFET, TFET, CNTFET. Among these, the FinFET emerges as one of the promising devices which can replace the CMOS due to its low leakage in the nanometer regime. The electronics devices are nowadays more compact and efficient in terms of battery consumption. The CMOS SRAMs have been replaced by the FinFET SRAMs due to the scaling limitations of the CMOS. Two FinFET SRAM cells have been which power efficient are and having high stability. Performance comparison of these cells has been done to analyze the leakage power and the static noise margins. The simulation of the cells is done at 20 nm FinFET technology. It has been analyzed that the write margin of improved 9T SRAM cell achieves an improvement of 1.49x. The read margin is also showing a drastic improvement over the existing cells which has been compared in the paper. The hold margin was found to be better in the case of the proposed SRAM cell at 0.4 V. The gate length has been varied to find the effect on read margin with gate length.

Magnetic Skyrmions: Recent advances and applications

Magnetic skyrmions are particle-like, nanometer-sized topological spin textures observed in several magnetic materials. They have emerged as an alternative to conventional spintronic memories and domain walls (DWs) and offer high storage density, more robust stability, low critical currents, and increased scalability. Recent advances have set the stage for their use in quantum computing, logic circuits, and neuromorphic computing. With the aid of electrical methods, it is possible to precisely create, manipulate, and destroy skyrmions in device-compatible materials. However, the maximum speed achievable by magnetic skyrmions and the reliable detection of data have been restricted by the skyrmion Hall effect (SkHE). Other issues include a low read margin and a lack of proper skyrmion motion control in nanowires. Most of these can be addressed by exploiting novel materials, such as antiferromagnets; employing specialized fabrication techniques; tuning driving current profiles; and circuit-level engineering. In this article, theoretical and experimental breakthroughs and challenges relevant to magnetic skyrmions and their applications in data storage, logic computing, and neuromorphic computing are highlighted.

A nonlinear resistive switching behaviors of Ni/HfO2/TiN memory structures for self-rectifying resistive switching memory

This work reports forming free/self-rectifying resistive switching characteristics and dependency of the top electrode (TE) of a crystalline HfO2-based resistive switching memory device. In the memory cells, nonlinear bipolar resistive switching characteristics, i.e., an asymmetric current-voltage curve like the Schottky diode, was observed. In addition, the device exhibits resistive switching behaviors without forming process, which makes it possible to switch the resistance state under ultra-low current levels of <10 nA. In addition, compared to the resistive switching of the proposed resistive switching memory devices with different TEs, the VSET was decreased when using TE with lower work function, and the height read margin was obtained in the sample with the Ni TE, covering over 56 × 56 arrays. Consequently, these results indicate that the interface control resistive switching properties in memory structures having the Schottky junction warrant the realization of selector-free resistive switching memory cells in a high-density crossbar array.

In‐Depth Analysis of One Selector–One Resistor Crossbar Array for Its Writing and Reading Operations for Hardware Neural Network with Finite Wire Resistance

This work provides a comprehensive analytical analysis of one‐selector‐one‐resistor (1S1R) crossbar array (CBA) device for hardware neural network (HNN) applications. Simplified analytical device models are prepared from a particular 1S1R device to validate the analysis. The read margin (RM) analysis results show that the V/3 voltage scheme and reduced selector leakage are necessary to maximize the RM and maximum operable size N of the CBA, where N indicates the number of wires (word line or bit line). The write margin (WM) analysis results show that the unwanted switching of the unselected cell during the write operation is unlikely in the 1S1R CBA even with a large N value, despite a voltage drop along the interconnection wire. The analysis of simultaneous multiply‐and‐accumulate operations is conducted using the analytical method to examine the influence of voltage drop according to the wire and memory cells in HNN applications. Reducing the wire resistance and on‐state conductance increases the available N value when the selector operates near the threshold conditions. The proposed analytical model can estimate the maximum accuracy degradation of the HNN through the involvement of the unintentional voltage drop.

Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports

In-memory computing establishes a new and promising computing paradigm aimed at solving problems caused by the von Neumann bottleneck. It eliminates the need for frequent data transfer between the memory and processing modules and enables the parallel activation of multiple lines. However, vertical data storage is generally required, increasing the implementation complexity for the SRAM writing mode. This article proposes a 10-transistor (10T) SRAM to omit vertical data storage and improve the stability of in-memory computing. A cross-layout of the word line enables arrays with multirow or multicolumn parallel activation to perform vector logic operations in two directions. In addition, the novel horizontal read channel allows matrix transposition. By reconfiguring the data lines, sense amplifiers, and multiplexing read ports, the proposed SRAM can be regarded as a content-addressable memory (CAM), and its symmetry provides selectable data search by column or by row according to the application that easily fits the SRAM storage mode without additional data adjustments. A proposed self-termination structure aims to decrease search energy consumption by approximately 38.5% at 0.9 V at the TT process corner. To verify the effectiveness of the proposed design, a 4 Kb SRAM was implemented in 28-nm CMOS technology. The read margin of the proposed 10T SRAM cell is three times higher than that of the conventional 6-transistor cell. At 0.9 V, logic operations can be performed at approximately 300 MHz, and binary CAM search operations are achieved at approximately 260 MHz with around 1 fJ of energy consumption per search/bit.

Memristive devices based on Cu-doped NbOx films with large self-rectifying ratio

To address the problem of sneak currents in large-scale crossbar arrays without extra access devices like transistors or selectors, memristive devices with self-rectifying characteristics are highly desired. Herein, memristive devices of Pt/Cu-NbOx/TiN with a large rectification ratio (~1.43 × 105 at ±2 V) are realized in Cu-doped NbOx thin films. The large rectification ratio is due to the large Schottky barrier height at the Pt/Cu-doped NbOx interface, which is closely related to the changes of the band structure through Cu doping. More importantly, the devices can facilitate the fabrication of memristive crossbar arrays whose scale can reach maximal 486 × 486 (~230 kbits) with 10% read margin. This work clearly proves the feasibility of the self-rectifying memristive devices for bio-inspired computing.