RC Low-pass Filter Research Articles

A 25-Gb/s Avalanche Photodetector-Based Burst-Mode Optical Receiver With 2.24-ns Reconfiguration Time in 28-nm CMOS

This paper describes an avalanche photodetector (APD)-based optical receiver, applicable to the burst-mode operation, in 28-nm CMOS technology. With the aims of benefiting the overall optical link power efficiency and link bandwidth, the optical receiver is designed to have high sensitivity and high reconfiguration speed for burst-mode operation. The sensitivity of the receiver is optimized by adjusting the responsivity of APD via its reverse bias voltage, which leads to the highest signal-to-noise ratio (SNR) at the front end. The two-tap feed-forward equalization (FFE), along with two-tap decision feedback equalization, is implemented in a current-integrating fashion to further improve the sensitivity with superior power efficiency to their resistively loaded counterparts. Integrating dc comparator and integrating amplitude comparator are proposed to replace the conventional RC low-pass filters and peak detectors, respectively, in extracting the information of dc offset and signal amplitude within two unit intervals (UIs), empowering significant acceleration of the burst-mode reconfiguration. When the APD is biased at −16 V, its overall responsivity at 1310 nm is 4 A/W, and the optical receiver achieves bit-error-rate (BER) better than 10−12 at −16-dBm optical modulation amplitude, 2.24-ns reconfiguration time with 5-dB dynamic range, and 1.37-pJ/b energy efficiency at 25 Gb/s.

Numerical Simulation of Second-Order Microfluidic Filter

In this paper, we present a microfluidic filter to improve mixing index and eliminate the pulsatile component within microfluidic devices, which is similar to a second-order RC low-pass filter in electronics. COMSOL Multiphysics, a kind of simulation software, is used to evaluate the analytical method and the efficiency of the device. Compared with the results obtained from the equivalent circuit theory, the simulation method has been verified. In addition, the equivalent circuit theory, in other words the fluid dynamical equivalent of Ohm’s law, is adopted to make the theoretical analysis. This microfluidic filter is equipped with multiple simple channels and microcavities having elastic membrane at the top layer, just like the series–parallel connection of resistors and capacitors. Based on the results, one microcavity is equivalent to first-order filter and two microcavities in series equal second-order filter which shows the better filtering effect. Actually, when the driving frequency exceeds 60 Hz, this device can export almost steady fluid. The mixing effect is improved compared with the simple microfluidic junctions. The combined application of microfluidics and equivalent circuit theory will gain insightful ideas and practical design methods for developing unique microfluidic devices to address a broad range of biological and chemical challenges.

Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI

Recent progress in continuous-time (CT) Delta-Sigma modulators (DSMs) research has shown that applying a passive RC low-pass filter (LPF) in the feedback path can significantly improve the power efficiency of a CT DSM. On the other hand, to achieve high performance, a CT DSM faces the adverse effects of clock jitter, intersymbol interference (ISI), or degradation of antialiasing ability. These challenges are extremely difficult to tackle simultaneously without consuming excessive power. This paper proposes a Gm-C DSM with a combined RC and switched-capacitor LPF frontend stage to achieve a high performance against aliasing, clock jitter, and ISI simultaneously while having an extremely low power consumption. Transistor-level simulations on an audio band modulator and a 10-MHz bandwidth modulator are given, verifying the high immunity of the proposed circuit to clock jitter, ISI, and aliasing while attaining a power efficiency up to 7.4 fJ/conversion step.

Improving Power Efficiency for Active-<italic>RC</italic> Delta-Sigma Modulators Using a Passive-<italic>RC</italic> Low-Pass Filter in the Feedback

This brief presents a technique to improve the power efficiency of an active- RC 1-bit continuous-time Delta-Sigma modulator (DSM). A passive- RC low-pass filter (LPF) is used in feedback after the 1-bit digital-to-analog converter (DAC). The LPF smooths out the rail-to-rail sharp edges of the DAC output to reduce the signal-swing and slew-rate requirements of the first amplifier in DSM. The LPF is also utilized to contribute a pole to the loop response of the modulator. It does not require a compensation filter and reduces the order of the active part of the loop filter. A third-order DSM was designed in a 0.18- ${\mu }\text{m}$ CMOS process. Measurement results show that it can achieve 79.1-dB SNDR over 100-kHz bandwidth while consuming only 59.1 ${\mu }\text{W}$ .

0.6 V, 116 nW Neural Spike Acquisition IC with Self-Biased Instrumentation Amplifier and Analog Spike Extraction.

This paper presents an ultralow power 0.6 V 116 nW neural spike acquisition integrated circuit with analog spike extraction. To reduce power consumption, an ultralow power self-biased current-balanced instrumentation amplifier (IA) is proposed. The passive RC lowpass filter in the amplifier acts as both DC servo loop and self-bias circuit. The spike detector, based on an analog nonlinear energy operator consisting of a low-voltage open-loop differentiator and an open-loop gate-bulk input multiplier, is designed to emphasize the high frequency spike components nonlinearly. To reduce the spike detection error, the adjacent spike merger is also proposed. The proposed circuit achieves a low IA current consumption of 46.4 nA at 0.6 V, noise efficiency factor (NEF) of 1.81, the bandwidth from 102 Hz to 1.94 kHz, the input referred noise of 9.37 μVrms, and overall power consumption of 116 nW at 0.6 V. The proposed circuit can be used in the ultralow power spike pulses acquisition applications, including the neurofeedback systems on peripheral nerves with low neuron density.

A Gm-C Delta-Sigma Modulator With a Merged Input-Feedback Gm Circuit for Nonlinearity Cancellation and Power Efficiency Enhancement

Traditionally, a transconductor-C (Gm-C)-based delta sigma modulator (DSM) has its performance limited by the nonlinearity of its Gm circuits. To achieve sufficient linearity, source degeneration is typically applied to a Gm circuit, which inevitably reduces the Gm circuit’s transconductance and thermal noise efficiencies. This paper presents new ways to change this paradigm. First, a DSM topology that has a passive RC lowpass filter (LPF) in its feedback is applied. We place the cutoff frequency of the LPF at the signal band edge to realize a pole of the DSM’s loop filter, thus reducing the power consumption. The LPF also suppresses the high-frequency components of quantization noise, enabling us to use a nonlinear Gm circuit in the DSM’s feedback while not causing quantization noise to fold into the signal band. With matched transfer characteristics and inputs, the input and feedback Gm circuits have their nonlinearities canceled with each other. Second, a merged input-feedback Gm circuit with shared degeneration resistors is proposed, which has high transconductance and noise efficiencies and simultaneously allows large input and feedback signals. A prototype DSM fabricated in a 0.18- $\mu \text{m}$ CMOS process demonstrates the nonlinearity cancellation and power efficiency of the proposed methods.

Bandwidth Analysis of RF-DC Converters Under Multisine Excitation

The use of multisine signals to improve the efficiency of wireless power transfer (WPT) for low average received power was proposed recently. Several measurement-based studies illustrated the gain that can be achieved for different circuit or waveform instances, focusing on the impact of a time-varying amplitude on the rectifying efficiency. This paper first establishes a model enabling a thorough analysis of the multisine-based WPT system focusing on the bandwidth of the signal and the rectifier. This model enables a codesign of signal and rectifier for optimal WPT. The proposed model provides insight into the output voltage and power, as a function of the input waveform for different circuit models. By including the input matching and the clamper, our model is generic and can include a wide range of rectifiers with different voltage multiplication approaches. The key insight gained from our analysis is that there is a tradeoff between the frequency spacing of the tones of the multisine signal and the cut-off frequency of the low-pass RC filter, as a main property of the rectifier circuit. Our model predicts the measured power conversion efficiency and voltage with an error below 0.1 and 0.2 V, respectively.

Vibration Based Energy Harvesting Interface Circuit using Diode-Capacitor Topologies for Low Power Applications

<span>A battery-less energy harvesting interface circuit to extract electrical energy from vibration has been proposed in this paper for low power applications. The voltage doubler integrated with DC – DC boost converter circuits were designed and simulated using MultiSIM software. The circuit was then fabricated onto a printed circuit board (PCB), using standard fabrication process. The Cockcroft Walton doubler was chosen to be implemented in this study by utilizing diode-capacitor topologies with additional RC low pass filter. The DC – DC boost converter has been designed using a CMOS step -up DC – DC switching regulators, which are suitable for low input voltage system. The achievement of this interface circuit was able to boost up the maximum voltage of 5 V for input voltage of 800 mV.</span>

Four-Quadrant Time-Division Multiplier without Using Any Reference Clock

ABSTRACTTime-division multiplier (TDM) can be developed using triangular wave or sawtooth wave as reference clock. However, Rathor and Bhattacharya developed a TDM without using any reference clock. Rathore–Bhattacharya multiplier is modified/redesigned with a minimum number of components, and is given in this paper as a design idea. The proposed circuit consists of one difference integrator, two comparators, one control amplifier, and an RC low-pass filter. The designed circuit uses only four op-amps and hence a single-quad op-amp IC LM324 can be used for low-cost applications. Verification of the feasibility of circuit design is established by the way of test results on prototypes.

Pencil-on-Paper Capacitors for Hand-Drawn RC Circuits and Capacitive Sensing

Electronic capacitors were constructed via hand-printing on paper using pencil graphite. Graphite traces were used to draw conductive connections and capacitor plates on opposing sides of a sheet of standard notebook paper. The paper served as the dielectric separating the plates. Capacitance of the devices was generally < 1000 pF and scaled with surface area of the plate electrodes. By combining a pencil-drawn capacitor with an additional resistive pencil trace, an RC low-pass filter was demonstrated. Further utility of the pencil-on-paper devices was demonstrated through description of a capacitive force transducer and reversible chemical sensing. The latter was achieved for water vapor when the hygroscopic cellulose matrix of the paper capacitor’s dielectric adsorbed water. The construction and demonstration of pencil-on-paper capacitive elements broadens the scope of paper-based electronic circuits while allowing new opportunities in the rapidly expanding field of paper-based sensors.

Time-dependent solutions for a stochastic model of gene expression with molecule production in the form of a compound Poisson process.

We study a stochastic model of gene expression, in which protein production has a form of random bursts whose size distribution is arbitrary, whereas protein decay is a first-order reaction. We find exact analytical expressions for the time evolution of the cumulant-generating function for the most general case when both the burst size probability distribution and the model parameters depend on time in an arbitrary (e.g., oscillatory) manner, and for arbitrary initial conditions. We show that in the case of periodic external activation and constant protein degradation rate, the response of the gene is analogous to the resistor-capacitor low-pass filter, where slow oscillations of the external driving have a greater effect on gene expression than the fast ones. We also demonstrate that the nth cumulant of the protein number distribution depends on the nth moment of the burst size distribution. We use these results to show that different measures of noise (coefficient of variation, Fano factor, fractional change of variance) may vary in time in a different manner. Therefore, any biological hypothesis of evolutionary optimization based on the nonmonotonic dependence of a chosen measure of noise on time must justify why it assumes that biological evolution quantifies noise in that particular way. Finally, we show that not only for exponentially distributed burst sizes but also for a wider class of burst size distributions (e.g., Dirac delta and gamma) the control of gene expression level by burst frequency modulation gives rise to proportional scaling of variance of the protein number distribution to its mean, whereas the control by amplitude modulation implies proportionality of protein number variance to the mean squared.

Resistor-less charge sensitive amplifier for semiconductor detectors

A new concept of a Charge Sensitive Amplifier without a high-value resistor in the feedback loop is presented. Basic spectroscopic parameters of the amplifier coupled to a coaxial High Purity Germanium detector (HPGe) are discussed. The amplifier signal input is realized with an n-channel J-FET transistor. The feedback capacitor is discharged continuously by the second, forward biased n-channel J-FET, driven by an RC low–pass filter. Both the analog—with a standard spectroscopy amplifier and a multi-channel analyzer—and the digital—by applying a Flash Analog to Digital Converter—signal readouts were tested. The achieved resolution in the analog and the digital readouts was 0.17% and 0.21%, respectively, at the Full Width at Half Maximum of the registered 60Co 1332.5keVgamma line.

9.5 mW fully integrated K ‐band on–off keying receiver with −47.6 dBm sensitivity and 600 Mbit/s data rate in 90 nm CMOS

A K-band on–off keying (OOK) receiver implemented in tsmcTM 90 nm CMOS process is proposed. The proposed OOK receiver consists of a two-stage wideband low-noise amplifier, a single-to-differential envelop detector with RC lowpass filter and a 62.6 dB three-stage variable gain amplifier and DC offset compensation circuit. The OOK receiver achieved a sensitivity of −47.6 dBm at 600 Mbit/s data rate under a pseudo-random binary sequence 29–1 pattern. The receiver consumes a low power of 9.5 mW, which minimum average power is only 15.86 nW at the input power of −47.6 dBm. The chip area including test pads is 1 × 0.81 mm2.

Analog Multiplier Based Single Phase Power Measurement

Present paper proposes a power measurement technique of a single phase electrical load. The proposed method is a low cost power measurement technique. The load which is taken into consideration is either resistive load such as bulb or inductive load like single phase induction motor. This method is based on a low cost analogue IC (AD633) which does the analogue multiplication of the two input signals. In fact, AD633 is well suited for applications such as power measurement, modulation and demodulation, automatic gain control, voltage-controlled amplifiers, and frequency doublers. In present work AD633 is employed for power measurement. The AD633 output voltage give the multiplication of corresponding current and voltage signals of the load and produces pulsating signal/voltage at the double of the supply frequency. The higher frequency output of AD633 is attenuated by a low pass filer of an appropriate cut-off frequency (90 Hz). The corresponding DC component of the multiplier IC output obtained at the output of the active RC low- pass filter is found to be proportional to the average load power consumed. The output of RC low pass filter was plotted against different values of load using MATLAB code. The linearity of these plots was checked through the linear curve fit and the original plots for the validation purposes

Optimized Wireless Stethoscope Using Butterworth Filter

Acoustic stethoscope is a primary diagnostic tool used by doctors for effective analysis of various diseases. But, it suffers defects such as low level heart sounds and presence of murmurs. This project aims at developing ‘Noise removal in stethoscope using Butterworth filter’. In this, the low level heart sounds were amplified with high gain pre-amplifier circuit. A review of basic filters like low pass RC filter, Butterworth filter, Chebyshev filter and Bessel filter are done for elimination of murmurs and best suited filter is suggested. Finally, amplified noise free heart sounds are simulated using Proteus 7.4. The results prove that efficient filter for designing is ‘Butterworth filter’.

A 100–800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving <formula formulatype="inline"><tex Notation="TeX">$<-$</tex></formula>40 dBc for ALL Harmonics

Radio transceivers capable of dynamic spectrum access require frequency-agile transmitters with a clean output spectrum. High- Q filters are difficult to implement on chip and have limited tuning range. Transmitters with high linearity and broadband harmonic rejection can be more flexible and require less filtering. However, traditional harmonic rejection mixers suppress only a few harmonics. This paper presents an 8-path polyphase transmitter, which exploits mixer-LO duty-cycle control and a tunable first-order RC low-pass filter to suppress ALL harmonics to below -40 dBc. The optimum duty-cycle theoretically is 43.65% and a resolution of better than 0.1% is required to keep the spread in harmonic rejection within 1 dB. We propose a simple monotonic duty-cycle control circuit and show by design equations and measurements that it achieves the required resolution over three octaves of frequency range. Also, analysis indicates that LO duty-cycle reduction compared with 50% improves power upconverter efficiency. A transmitter realized in 0.16- μm CMOS works from 100 to 800 MHz at a maximum single-tone output power of 10.8 dBm with an efficiency of 8.7%, outperforming previous designs. The OIP3 is >21 dBm, while the LO leakage and image rejection is better than -45 dBc.

A sine-LO square-law harmonic-rejection mixer—theory, implementation, and application

A square-law harmonic-rejection mixer (SL-HRM) driven by a sine local oscillator (LO) is proposed for wideband and tunable rejection of all LO harmonics. The key performances including the gain, noise figure (NF), input-referred third-order intercept point (IIP3), and harmonic rejection ratio (HRR) with respect to the amplitude and purity of the sine-LO are analyzed. In the circuit level, the SL-HRM incorporates a voltage-boosted technique to surmount the gain and NF penalties of square-law mixing, while guaranteeing the device reliability via introducing a supply startup circuit and a node-voltage protection circuit. The entailed high-purity sine-LO is achieved via a digital-intensive square-to-sine LO generator plus a passive- RC low-pass filter. Fabricated in 65-nm CMOS, the VHF-/UHF-band SL-HRM has a tunable gain of 1-13 dB, associated with an NF of 27-15 dB, under an LO amplitude of 50-200 mV pp. The IIP3 is stable within from +6.5 to +7.6 dBm, as expected. The tunable HRR3 and HRR5 are 13-40 dB and 17-45 dB, respectively. The mixer core consumes 7.5 mW at 2.5 V, while the LO generator draws 3-6 mW at 1.2 V. The total active area is just 0.042 mm2.

1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS

This paper describes the front-end of a fully integrated analog interface for 300 MSps, high-definition video digitizers in a system on-chip environment. The analog interface is implemented in a 1.2 V, 65-nm digital CMOS process and the design minimizes the number of power domains using core transistors only. Each analog video receiver channel contains an integrated multiplexer with a current-mode dc-clamp, a programmable gain amplifier (PGA) and a pseudo second-order RC low-pass filter. The digital charge-pump clamp is integrated with low-voltage bootstrapped tee-switches inside the multiplexer, while restoring the dc component of ac-coupled inputs. The PGA contains a four-stage fully symmetric pseudo-differential amplifier with common-mode feedforward and inherent common-mode feedback, utilized in a closed loop capacitive feedback configuration. The amplifier features offset cancellation during the horizontal blanking. The video interface is evaluated using a unique test signal over a range of video formats for INL+/DNL+, INL-/DNL-. The 0.07-0.39 mV INL, 2-70 μV DNL, and 66-74 dB of SFDR, enable us to target various formats for 9-12 bit Low-voltage digitizers.

$RC$ Model for Frequency Dependence of Split $C\hbox{--}V$ Measurements on Bare SOI Wafers

The feasibility of split C-V measurements for direct evaluation of carrier mobility in as-fabricated silicon-on-insulator wafers has been demonstrated. Here, we complete this letter by modeling the frequency dependence of capacitance curves. The peculiarity of the pseudo-MOSFET (Ψ-MOSFET) configuration with respect to standard MOSFET comes from the possible distribution of mobile carriers beyond the source and drain contacts. This implies a variation in charge spreading and capacitance with frequency that we address with an RC low-pass filter model. Experimental C-V measurements with one and two probes were used for validation of the proposed model.

Active matrix touch sensor detecting time-constant change implemented by dual-gate IGZO TFTs

The dual-gate IGZO TFT is proposed to be used in an active matrix touch sensing circuit. The circuit contains only one TFT with a RC low-pass filter, since the dual-gate IGZO TFT can be controlled by both its top and bottom gates. The simplest structure maximizes the sensing pad area in the pixel. A touch event on the sensing pad forms a capacitance and thus increases the RC time-constant of the scan pulse fed to the gate of TFT. Thus, a significant transient ON current is generated to be the sensing signal. The current is so large that it can be easily read out and thus the power and cost of peripheral ICs can be reduced. In this paper, the robustness of the circuit to environment in operations is discussed.