Abstract
This paper presents an ultralow power 0.6 V 116 nW neural spike acquisition integrated circuit with analog spike extraction. To reduce power consumption, an ultralow power self-biased current-balanced instrumentation amplifier (IA) is proposed. The passive RC lowpass filter in the amplifier acts as both DC servo loop and self-bias circuit. The spike detector, based on an analog nonlinear energy operator consisting of a low-voltage open-loop differentiator and an open-loop gate-bulk input multiplier, is designed to emphasize the high frequency spike components nonlinearly. To reduce the spike detection error, the adjacent spike merger is also proposed. The proposed circuit achieves a low IA current consumption of 46.4 nA at 0.6 V, noise efficiency factor (NEF) of 1.81, the bandwidth from 102 Hz to 1.94 kHz, the input referred noise of 9.37 μVrms, and overall power consumption of 116 nW at 0.6 V. The proposed circuit can be used in the ultralow power spike pulses acquisition applications, including the neurofeedback systems on peripheral nerves with low neuron density.
Highlights
Ultralow power consumption is highly required to avoid overheating surrounding tissues in many neuroprosthetic devices, as well as to operate the device for long term with limited power capacity under implanted condition [1]
We propose an ultralow power neural spike acquisition integrated circuit (IC) with analog spike extraction supplied with 0.6 V
The central node between the two pseudo-resistors ROUT is connected to gate of n-type metal oxide semiconductor semiconductor (NMOS)
Summary
Ultralow power consumption is highly required to avoid overheating surrounding tissues in many neuroprosthetic devices, as well as to operate the device for long term with limited power capacity under implanted condition [1]. To record the low frequency neural signals, high power and area consumptions are required to reduce the flicker noises. The CBIA gain is mostly determined by the ratio of resistors and affected by the corner variations of the transistor parameters, including source and drain resistances It has an open-loop operation, exhibiting a wider bandwidth without frequency compensation. The ultralow power analog domain NEO composed of a low-voltage open-loop differentiator, and an open-loop gate-bulk input multiplier is designed to emphasize the high frequency spike components nonlinearly. This paper is organized as follows: Section 2 details the design, operation principle, and circuit of the proposed ultralow power neural spike acquisition IC with analog spike extraction.
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