Abstract
This brief presents a technique to improve the power efficiency of an active- RC 1-bit continuous-time Delta-Sigma modulator (DSM). A passive- RC low-pass filter (LPF) is used in feedback after the 1-bit digital-to-analog converter (DAC). The LPF smooths out the rail-to-rail sharp edges of the DAC output to reduce the signal-swing and slew-rate requirements of the first amplifier in DSM. The LPF is also utilized to contribute a pole to the loop response of the modulator. It does not require a compensation filter and reduces the order of the active part of the loop filter. A third-order DSM was designed in a 0.18- ${\mu }\text{m}$ CMOS process. Measurement results show that it can achieve 79.1-dB SNDR over 100-kHz bandwidth while consuming only 59.1 ${\mu }\text{W}$ .
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