Clock Frequency Research Articles

Modeling Of Mask Detection Systems, Distance Between Objects And Facial Recognition Using The Tiny-YOLOV4 Method, Convolutional Neural Network, And Viola Jones

The development of technology is currently increasing very rapidly, the latest technology such as Face Detection and Face Recognition in public facilities has been widely applied, such as cameras for attendance, facial detection devices as mobile phone security and various other new innovations in the field of technology. The purpose of creating this model is to determine the distance, and the use of masks in public places and to determine the performance when the two algorithms between Tiny-YOLOV4 and Viola Jones are combined. This method uses CPU testing with a clock speed of 2.9 GHz and GPU with a clock speed of 1590 MHz with an accuracy level of 92.6% for mask object detection and 90.67% for face recognition with a maximum distance in front of the camera for human detection is 830 centimeters, mask detection 730 centimeters, and face recognition 530 centimeters. The results of the study produced an accuracy of 92.6% for mask detection and an accuracy of 90.67% for face recognition at maximum distances of 730 cm and 530 cm respectively. The conclusion shows that this system is effective for detecting masks, faces, and distance, providing a significant tool for monitoring compliance in public spaces. Implementing this system can serve as a preventive measure for potential future pandemics

Watch Out for the Inherent Vulnerabilities in Developing Multi-tenant Cloud-FPGA: Communication Protocols

As FPGAs are being deployed in the cloud infrastructure for acceleration, the technology of multi-tenant FPGA has emerged as a topic of interest. This development has drawn considerable attention to its security issues. While previous research primarily focused on the security of applications, there has been limited exploration of the vulnerabilities inherent in FPGA IPs. In our work, we examine the vulnerabilities of two widely used data transmission protocols in modern FPGAs: the Advanced eXtensible Interface (AXI) and Peripheral Component Interconnect Express (PCIe). Our experiments, conducted with commercial FPGA development kits, launched fault injection attacks through the shared power distribution network (PDN). Through non-invasive electromagnetic (EM) trace measurement, we characterize the voltage fluctuation across various attack patterns. Subsequently, we simulate real-world data transfers using two crafted datasets with different statistical characteristics. The experimental results demonstrate the unique security vulnerabilities of the current AXI and PCIe protocols in the context of a multi-tenant cloud-FPGA. In response to such vulnerability, we further propose two defense strategies: InChAXI that utilizes integrity checking for AXI-based data, and FCPCIe that employs frequency scaling for PCIe-based data. The performance evaluation demonstrates that our proposed defenses can significantly reduce the fault injections on the AXI-based data transmission by 705 times with small overheads – 0.5% in hardware footprint and 7.9% in latency, respectively. On the other hand, FCPCIe effectively prevents the fault injection attack during the PCIe-based data transmission by reducing the user clock frequency, while incurring a 10.13% overhead on data throughput.

Foundry fabricated compact slow-light Mach-Zehnder modulator and photodetector for on-chip analog photonic computing

This work presents a scaling pathway of on-chip analog photonic computing using foundry-fabricated silicon electro-optic (EO) slow-light Mach-Zehnder modulators (SL-MZMs) and compact Ge photodetectors (PDs) to construct a computing unit. Two SL-MZMs with phase shifter (PS) lengths of 500 μm and 150 μm are studied in this work. The bit resolution, nonlinearity, clock frequency, and power consumption of the photonic computing link, including an RF amplifier, on-chip SL-MZM, and a PD, are thoroughly investigated. The computing link using the SL-MZM with 500 μm has demonstrated a low normalized mean square error (NMSE) of 0.0305 at 8-bit resolution under 3.2 GHz clock frequency. Under the setting of 6-bit resolution at a clock frequency of 800 MHz, high computing accuracy was achieved with a measured NMSE of 0.0018 using the SL-MZM with 150 μm PS length. Using the Google Speed Commands dataset to run a voice keyword spotting task, we determine that 6-bit resolution operating at 3.2 GHz achieves the optimal power-accuracy trade-off. We show a 20× improvement in energy efficiency and a 3.35× improvement in area efficiency compared to NVIDIA V100 GPU [“Volta: Performance and programmability,” IEEE Micro 38(2), 42 (2018)10.1109/MM.2018.022071134 ]. These results show that our compact SL-MZMs and PDs promise to scale up photonic computing for practical machine-learning applications.

Timing issues on power side-channel leakage of advanced encryption standard circuits designed by high-level synthesis

In recent years, field programmable gate array (FPGA) have been used in many internet of things (IoT) devices and are equipped with cryptographic circuits to ensure security. However, they are exposed to the risk of cryptographic keys being stolen by side-channel attacks. Countermeasures against side-channel attacks have been developed, but they are becoming more of a threat to IoT devices due to the diversity of attacks. Therefore, it is necessary to understand the basic characteristics of side-channel attacks. Therefore, this study clarifies the relationship between two timing issues, the clock period of the circuit and the power sampling interval, and the amount of side-channel leakage. We design seven advanced encryption standard (AES) circuits with different clock periods and conduct empirical experiments using logic simulations to clarify the correlation between the two timings and the amount of side-channel leakage. T-test is used to evaluate the leakage amount, which is evaluated based on four metrics. From the results, we argue that the clock period and sampling interval do not interfere with each other in the side-channel leakage amount.

Design of a low-power Digital-to-Pulse Converter (DPC) for in-memory-computing applications

Data converters such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital-to-time converters (DTCs), time-to-digital converters (TDCs), among others, are considered some of the most essential blocks in the field of integrated circuit design. In this work, we introduce a novel type of data converter known as the Digital-to-Pulse converter (DPC) and present its novel analog flow circuit implementation. The DPC system is a critical component in emerging artificial neural network accelerators and in-memory computing systems. The DPC system presented in this study offers two distinct operating modes. The first mode is the generation of a single pulse with a width that is modulated by the digital input. The second mode is an n-bit digital to discrete pulse converter, where the number of generated pulses is directly related to the value of the digital input. The proposed DPC system offers designers a high level of flexibility in shaping the characteristics of the output pulses, including the number of pulses, pulse width, and pulse amplitude. This empowers designers to accommodate different application requirements and scenarios effectively. The proposed circuit has been verified and tested using Virtuoso Cadence circuit tools in 180 nm CMOS technology with post-layout simulation and analysis. The results indicate a significant enhancement in average power consumption (∼12×), layout area (∼5×), and Latency (∼1.4×) with the proposed system compared to the digital Register Transfer Level (RTL) implementation under a power supply of 1.8V and a clock frequency of 1 GHz in the Application Specific Integrated Circuits (ASIC) flow. This demonstrates the suitability of the proposed system for low-power and high-speed applications.

Broadband generation and tomography of non-Gaussian states for ultra-fast optical quantum processors

Quantum information processors benefit from high clock frequencies to fully harness quantum advantages before they are lost to decoherence. All-optical systems offer unique benefits due to their inherent 100-THz carrier frequency, enabling the development of THz-clock frequency processors. However, the bandwidth of quantum light sources and measurement devices has been limited to the MHz range, with nonclassical state generation rates in the kHz range. In this study, we demonstrated broadband generation and quantum tomography of non-Gaussian states using an optical parametric amplifier (OPA) as a squeezed light source and an optical phase-sensitive amplifier (PSA). Our system includes a 6-THz squeezed-light source, a 6-THz PSA, and a 66-GHz homodyne detector. We successfully generated non-Gaussian states at a 0.9 MHz rate with sub-nanosecond wave packets using a continuous-wave laser. The performance is currently limited by the jitter of superconducting detectors, restricting the usable bandwidth to 1 GHz. Our technique extends the bandwidth to GHz, potentially increasing non-Gaussian state generation rates for practical optical quantum processors using OPAs.

Temporal trends in weight-based disparities in physical fitness of children: 30-years of continuous surveillance through Slovenian national system

BackgroundObesity in childhood has deleterious consequences for health while improving physical fitness can significantly reduce health risks related to high body mass index. We aimed to examine the evolution of disparities in physical fitness based on weight status among 7–15-year-olds in Slovenia between 1989 and 2019 and compare these trends across sex, age and socioeconomic status.MethodsWe used annual data collected within the SLOfit monitoring system in the period between 1989 and 2019, totalling 4,256,930 participants (about 137 000 per year). We examined cardiorespiratory fitness (600-m run test), muscular fitness (60-s sit-ups, bent arm hang, and standing broad jump test) and skill-related fitness (backwards obstacle course, 60-m dash, arm plate tapping). We grouped children according to the IOTF cut-offs for BMI to those living with normal weight or excess weight and estimated changes in physical fitness over time by fitting quantile regression models separately by sex and age group, and then using segmented regression to identify the patterns of trends over time.ResultsWeight-based disparities in physical fitness were large in 1989 and have further increased by 2019. The increase in disparities was generally around 5 percentiles larger in boys, and 10–15-year-olds compared to younger children. It was particularly pronounced for body core strength and speed in boys (up to 15 and 19 percentiles, respectively) and upper body strength and speed among girls (up to 13 percentiles). Most of the increase in disparities in health-related fitness accumulated during the 2010s, when the fitness of children generally improved, but much less so in children living with excess weight.ConclusionsDespite recent improvements in population fitness levels, children with excess weight seem to be left behind, which adds to existing health inequalities. Our results should encourage policymakers to redesign policies aimed at promoting physical activity and enhancing physical fitness to make them more equitable and ultimately lead to reducing inequalities in fitness.

Improving PPP timing and time transfer based on signal distortion biases calibration

Abstract Precise point positioning (PPP) technology has been widely used for more than a decade in timing and time transfer. Pseudorange bias caused by signal distortion will reach up ±3 ns, which cannot be neglected in sub-nanosecond level PPP timing and time transfer. We propose to improve the performance of PPP timing and time transfer by considering signal distortion bias (SDB). In principle, SDB will affect PPP timing and time transfer by influencing the initial clock offset. Then, it is verified by theoretical and experimental analyses. The theoretical results show that the impact of SDB on PPP timing can reach up 1.8 ns in different regions. Also, the impact of SDB on time transfer can reach up 0.8 ns in different regions even if the baseline length and receiver types are the same. For experimental results, the accuracy of PPP timing and time transfer improves with SDB correction. For time transfer, the RMSs are reduced by 54.8%, 61.1% and 17.6% for GPS, BDS3 and Galileo in all links, respectively. The clock frequency consistency obtained from different systems has been improved. And the frequency stability of time link with Hydrogen clocks is improved by 53.0% at 10000s interval with SDB correction.

A hardware architecture for single and multiple ellipse detection using genetic algorithms and high-level synthesis tools

Ellipse detection techniques are often developed and validated in software environments, neglecting the critical consideration of computational efficiency and resource constraints prevalent in embedded systems. Furthermore, programmable logic devices, notably Field Programmable Gate Arrays (FPGAs), have emerged as indispensable assets for enhancing performance and expediting various processing applications. In the realm of computational efficiency, hardware implementations have the flexibility to tailor the required arithmetic for various applications using fixed-point representation. This approach enables faster computations while upholding adequate accuracy, resulting in reduced resource and energy consumption compared to software applications that rely on higher clock speeds, which often lead to increased resource and energy consumption. Additionally, hardware solutions provide portability and are suitable for resource-constrained and battery-powered applications. This study introduces a novel hardware architecture in the form of an intellectual property core that harnesses the capabilities of a genetic algorithm to detect single and multi ellipses in digital images. In general, genetic algorithms have been demonstrated to be an alternative that shows better results than those based on traditional methods such as the Hough Transform and Random Sample Consensus, particularly in terms of accuracy, flexibility, and robustness. Our genetic algorithm randomly takes five edge points as parameters from the image tested, creating an individual treated as a potential candidate ellipse. The fitness evaluation function determines whether the candidate ellipse truly exists in the image space. The core is designed using Vitis High-Level Synthesis (HLS), a powerful tool that converts C or C＋＋functions into Register-Transfer Level (RTL) code, including VHDL and Verilog. The implementation and testing of the ellipse detection system were carried out on the PYNQ-Z1, a cost-effective development board housing the Xilinx Zynq-7000 System-on-Chip (SoC). PYNQ, an open-source framework, seamlessly integrates programmable logic with a dual-core ARM Cortex-A9 processor, offering the flexibility of Python programming for the onboard SoC processor. The experimental results, based on synthetic and real images, some of them with the presence of noise processed by the developed ellipse detection system, highlight the intellectual property core’s exceptional suitability for resource-constrained embedded systems. Notably, it achieves remarkable performance and accuracy rates, consistently exceeding 99% in most cases. This research aims to contribute to the advancement of hardware-accelerated ellipse detection, catering to the demanding requirements of real-time applications while minimizing resource consumption.

Clock Gene Expression in Eel Retina and Hypothalamus: Response to Photoperiod and Moonlight.

Assessment of the clock genes, Period (Per) 1, Per2, Per3, and Cryptochrome (Cry) 2, Cry3, and Cry4, can help better understand eel spawning ecology. In this study, the circadian rhythm and moonlight effects of these clock genes in the eel retina and hypothalamus were analyzed. We examined clock gene expression patterns under 12 h light:12 h darkness (12L12D), constant darkness (DD), and constant light (LL) conditions; under short photoperiod (SP; 9L15D) and long photoperiod (LP; 15L9D), and during the new moon (NM) and full moon in male eels. Per2 expression increased after sunrise, Cry2, and Cry4 expression increased around sunset, and Per1, Per3, and Cry3 expression increased before sunrise. Under SP conditions, oscillations of retinal Per3 and Cry4, which did not occur under LP conditions, were generated. In addition, retinal Cry4 oscillation was generated under NM conditions. These results suggest that the retina of the eel may play an important role in regulating circadian rhythm, and migration is initiated by the synchronization of clock genes by moonlight, suggesting that photic signals are closely related to the migratory activity of the eel.

Real-time Blood Pressure Prediction on Wearable Devices using Edge Based Deep Neural Networks: A Hardware-software Co-design Approach

This paper presents the hardware realization of a real-time blood pressure (BP) prediction model for wearable devices, utilizing long short-term memory (LSTM) deep neural networks (DNNs). The proposed system uses both electrocardiogram (ECG) and photoplethysmogram (PPG) signal values for BP prediction. It aims to address the limitations of traditional BP measurement methods, providing a low error, minimal computational overhead, more accurate and convenient alternative system for individuals with hypertension or at risk for cardiovascular diseases. The utilization of split matrix approach leads to a reduction in hardware complexity across the entire system. This technique involves breaking down the larger weight matrices used in the computations of DNNs into smaller matrices. This fragmentation results in a decrease in the complexity of the hardware responsible for performing matrix vector multiplications (MVMs) within LSTMs. The resultant architecture of the predictive model gains several advantages, including a lowered level of complexity in terms of the space occupied by individual cells, decreased processing delay, and reduced power consumption. Furthermore, this approach enables the achievement of a notably improved minimum achievable clock period of 2.972 ns. This prediction model can operate locally on wearable devices, reducing the reliance on cloud computing and improving privacy and security. The performance evaluations are carried out using both analytical and implementation results. The results indicate that the proposed model can be practically applied to real-world problems and can potentially enhance the accuracy of various machine-learning tasks.

State‐of‐the‐Art 3DES Pipelined Cryptographic Engine Design Against Side‐Channel Attacks

ABSTRACTIn this paper, a high‐speed, low‐latency, and high‐security hardware‐implemented triple data encryption standard (3DES) cryptographic algorithm is proposed for securing data privacy. In order to achieve a high throughput for the 3DES architecture, the whole circuit is optimized with a 24‐stage pipelined design at first. For breaking the correlation between the processed data and power dissipation of the 3DES circuit against differential power analysis (DPA) attacks, two pseudo‐random number generators (PRNGs) are embedded to randomly alter the number of pipelined stages and data substitution locations within the 3DES circuit, respectively. Under such a circumstance, the proposed 3DES circuit is able to achieve high performance and strong robustness against DPA attacks without causing much overhead. As shown in the results, under the synthesis of SMIC 14‐nm process design kits (PDK), the clock frequency, area, power dissipation, and throughput of the proposed 3DES circuit, respectively, are achieved as 1.2 GHz, 26,435 m2, 21.05 mW, and 64 Gbps. Furthermore, when DPA attacks are executed on the proposed 3DES circuit, the corresponding secret key cannot be revealed even if 2 million plaintexts are enabled. In contrast, only 40,000 plaintexts are adequate to disclose the secret key of a regular pipelined 3DES circuit.

Design and Implementation of Image Acquisition and Signal Transmission Functions based on FPGA

Abstract In recent years, video network monitoring systems have evolved rapidly, from the first generation of digital-analogue systems to the fully IP-based systems. Based on the FPGA core, this design focuses on image acquisition and information transmission. The FPGA expansion board contains several peripheral modules, including the OV7670 camera captures images, DRAM stores data, and FIFO handles cross-clock domain signal transmission. While the reference clock is 40ns, in this system, the clock period is 20ns, making two clock cycles equal to one reference clock cycle. Then, two counters are used, one is the reference clock and another is the line synchronization (cnt1) to count 800 clock cycles per line. The end of a line is indicated by end_cnt0, and FIFO data is stored in SDRAM. Configuring the VGA display driver allows image data to be transmitted and displayed on the VGA screen. The system features a simple structure, high resource utilization, and strong reliability.

Charge pump-based PVT-resilient 45 nm CMOS dynamic comparator leveraging high speed and power efficiency

High-speed, low-power consumption, compact area, and high resolution are critical for analog /mixed signal applications. This article presents a novel design for a dynamic latch comparator that achieves exceptional speed, minimal power consumption, and a significantly reduced die area. The innovative comparator leverages a novel charge shared logic-based reset technique, which enables unparalleled speed and power efficiency. Rigorous simulations and analyses confirm that the delay time is drastically reduced compared to traditional dynamic latched comparators. The results clearly indicate that the proposed design exhibits high tolerance to PVT (process, voltage, and temperature) variations, making it highly suitable for mixed-signal applications. Designed and simulated using advanced 45 nm CMOS technology, the proposed circuit achieves an impressive delay of 18.5 ps and a remarkably low power consumption of 3.66 μW at a 1 V supply voltage and 1 GHz clock frequency.

PHOTONIC INTEGRATED CIRCUITS: GIANT LEAP IN COMPUTING TECHNOLOGY

There is a continued demand for increase in computing requirements from sensor, smartphones, to servers. However, the technology improvements in clock speed, power, and memory bandwidth from traditional electronic integrated circuits (EIC) has started to saturate. This has triggered further research in exploration of photon integrated circuits (PIC) that utilize photons (or particles of light) as opposed to electrons to form a functioning circuit. Research suggests that by integrating the benefits of EIC and PIC, one is able to harness the best of both worlds. The inherent advantages of photonics technology such as speed, energy-efficiency, and density, coupled with the advances in material technology, make them suitable to address the challenge of designing heterogeneous chips. This paper presents the fundamentals of the photonic technology, applicability to solving digital computing problems, ability to integrate into PICs, and its capability to complement electronic integrated circuits for powering the computing demands of emerging applications.

Dynamic Clock Switching Scheme for Enhanced Power Efficiency in System-on-Chip Architectures

High power consumption and thermal management are critical challenges in traditional System- on-Chip (SoC) architectures due to multiple active clock sources feeding individual IP blocks, even during idle states. This paper introduces a dynamic clock switching power-saving scheme that consolidates clock sources by dynamically switching to a single lower-frequency clock during low-power modes. A Clock Control Agent (CCA) monitors real-time operational status, power consumption, and performance needs, leveraging AI for predictive adjustments. Experimental results demonstrate a significant reduction in idle power consumption and improved thermal management, without compromising performance or data integrity. This scheme addresses inefficiencies in existing methods such as Dynamic Voltage and Frequency Scaling (DVFS) and clock gating, offering a robust and efficient solution for next-generation SoC designs.

A Mixed Approach for Clock Synchronization in Distributed Data Acquisition Systems.

Proper timing synchronization is important when data from sensors are acquired by different devices. This paper proposes a simple but effective solution for System on Chip (SoC) architectures that integrates a general-purpose Field Programmable Gate Array (FPGA) with a CPU. The proposed approach relies on a network synchronization protocol implemented in software, such as Network Time Protocol (NTP) or Precision Time Protocol (PTP), and uses the FPGA to generate a clock reference that is maintained in step with the synchronized system clock. The clock generated by the FPGA is obtained from the FPGA oscillator via appropriate fractional clock division. Clock drift is avoided via a software program that periodically compares the FPGA and the system counters, respectively, and adjusts the fractional clock divider in order to slightly adjust the FPGA clock frequency using a Proportional Integral controller. A specific implementation is presented on the RedPitaya platform, generating a 1 MHz clock in step with the NTP synchronized system clock. The presented system has been used in a distributed data acquisition system for fast transient recording in the neutral beam test facility for the ITER nuclear fusion experiment.

Efficient CRISPR/Cas9-mediated genome editing in the European corn borer, Ostrinia nubilalis.

The European corn borer (Ostrinia nubilalis) is an agricultural pest and burgeoning model for research on speciation, seasonal adaptation and insect resistance management. Although previous work in O. nubilalis has identified genes associated with differences in life cycle, reproduction, and resistance to Bt toxins, the general lack of a robust gene-editing protocol for O. nubilalis has been a barrier to functional validation of candidate genes. Here, we demonstrate an efficient and practical methodology for heritable gene mutagenesis in O. nubilalis using the CRISPR/Cas9 genome editing system. Precise loss-of-function (LOF) mutations were generated at two circadian clock genes, period (per) and pigment-dispersing factor receptor (pdfr), and a developmental gene, prothoracicotropic hormone (ptth). Precluding the need for a visible genetic marker, gene-editing efficiency remained high across different single guide RNAs (sgRNA) and germline transmission of mutations to F1 offspring approached 100%. When single or dual sgRNAs were injected at a high concentration, gene-specific phenotypic differences in behaviour and development were identified in F0 mutants. Specifically, F0 gene mutants demonstrated that PER, but not PDFR, is essential for normal timing of eclosion. PTTH F0 mutants were significantly heavier and exhibited a higher incidence of diapause. This work will accelerate future studies of gene function in O. nubilalis and facilitate the development of similar screens in other Lepidopteran and non-model insects.

Hardware implementation of bearing fault diagnosis using empirical mode decomposition

ABSTRACT This paper presents a comprehensive methodology for developing a vibration measurement system, with a primary focus on monitoring rolling element bearings, widely recognised as pivotal components in generic machine vibration monitoring. Through the utilisation of sensors to capture vibration data signals, the system aims to meticulously analyse these signals to discern any indications of bearing health deterioration, thus facilitating the early identification of potential pre-breakdown conditions. The proposed system initiates the process by internally decomposing the three-axis vibration signal, enabling subsequent transmission of processed data to a remote location for the identification of specific faults in the roller element bearings. Installation of a three-axis accelerometer on the bearing housing, positioned radially, facilitates the capture of raw vibration data along one axial and two radial directions. Moreover, efforts to enhance computational efficiency involve cascading multiple identical modules in a serial pipeline structure, allowing for iterative loop computation of intrinsic mode functions within Empirical Mode Decomposition (EMD). Real-time computation is achieved through this serial pipeline structure, necessitating two distinct clock frequencies: one at 12.5 MHz for sampling and storing 3-axis vibration data in ping pong buffers, and another at 40 MHz for reading and processing the data signal retrieved from these buffers. Validation of the proposed method is demonstrated through simulation results obtained via synthesised Verilog code on Xilinx Artix-7 FPGA (XC7A35T-1CPG236C), affirming its efficacy in real-time applications.

Энергоэффективность многоядерных процессоров: сравнительное исследование аппаратных технологий

Background: The constant increase in processing demand has prompted the development of multi-core processors, which are critical to obtaining high performance in a variety of computing devices. However, this growth in processing capacity comes at the expense of increased energy consumption, posing substantial problems for energy efficiency. Objective: The article will examine and compare several hardware solutions for improving energy efficiency in multi-core processors, offering a full overview of their effectiveness and application. Methods: We used a quantitative research methodology, simulating multi-core processing environments with various hardware optimization techniques such as Dynamic Voltage and Frequency Scaling (DVFS), Clock Gating, and Power Gating. Each technique was evaluated in a variety of operational circumstances to establish its effect on energy consumption and processing efficiency. Results: The findings show that DVFS provides significant energy savings with negligible performance trade-offs in cases with moderate workloads. In contrast, Clock Gating performed best in low workload settings, whereas Power Gating performed best in high-load conditions, dramatically reducing idle power consumption. Conclusion: The comparison research demonstrates that no single technique beats all others; rather, the choice of an effective energy efficiency strategy is significantly influenced by unique workload factors. A hybrid strategy, which combines both techniques depending on real-time workload demands, can greatly improve the energy efficiency of multi-core processors. This study advances our understanding of energy management in advanced computing systems, providing insights for future research and practical applications in the field of energy-efficient computing.