Rapid Thermal Processing Steps Research Articles

Boron Monolayer Doping: Role of Oxide Capping Layer, Molecular Fragmentation, and Doping Uniformity at the Nanoscale

AbstractDoping methodologies using monolayers offer controlled, ex situ doping of nanowires (NWs), and 3D device architectures using molecular monolayers as dopant sources with uniform, self‐limiting characteristics. Comparing doping levels and uniformity for boron‐containing monolayers using different methodologies demonstrates the effects of oxide capping on doping performances following rapid thermal anneal (RTA). Strikingly, for noncovalent monolayers of phenylboronic acid (PBA), highest doping levels are obtained with minimal thermal budget without applying oxide capping. Monolayer damage and entrapment of molecular fragments in the oxide capping layer account for the lower performance caused by thermal damage to the PBA monolayer, which results in transformation of the monolayer source to a thin solid source layer. The impact of the oxide capping procedure is demonstrated by a series of experiments. Details of monolayer fragmentation processes and its impact on doping uniformity at the nanoscale are addressed for two types of surface chemistries by applying Kelvin probe force microscopy (KPFM). These results point at the importance of molecular decomposition processes for monolayer‐based doping methodologies, both during preanneal capping step and during rapid thermal processing step. These are important guidelines to be considered for future developments of appropriate surface chemistry used in monolayer doping applications.

Structural and chemical evolution of the CdS:O window layer during individual CdTe solar cell processing steps

Oxygenated cadmium sulfide (CdS:O) is often used as the n-type window layer in high-performance CdTe heterojunction solar cells. The as-deposited layer prepared by reactive sputtering is XRD amorphous, with a bulk composition of CdS0.8O1.2. Recently it was shown that this layer undergoes significant transformation during device fabrication, but the roles of the individual high temperature processing steps was unclear. In this work high resolution transmission electron microscopy coupled to elemental analysis was used to understand the evolution of the heterojunction region through the individual high temperature fabrication steps of CdTe deposition, CdCl2 activation, and back contact activation. It is found that during CdTe deposition by close spaced sublimation at 600 °C the CdS:O film undergoes recrystallization, accompanied by a significant (∼30%) reduction in thickness. It is observed that oxygen segregates during this step, forming a bi-layer morphology consisting of nanocrystalline CdS adjacent to the tin oxide contact and an oxygen-rich layer adjacent to the CdTe absorber. This bilayer structure is then lost during the 400 °C CdCl2 treatment where the film transforms into a heterogeneous structure with cadmium sulfate clusters distributed randomly throughout the window layer. The thickness of window layer remains essentially unchanged after CdCl2 treatment, but a ∼25 nm graded interfacial layer between CdTe and the window region is formed. Finally, the rapid thermal processing step used to activate the back contact was found to have a negligible impact on the structure or composition of the heterojunction region.

Impact of varied sulfur incorporation on the device performance of sequentially processed Cu(In,Ga)(Se,S)2 thin film solar cells

In order to improve the performance of chalcopyrite Cu(In1 − x,Gax)(Se1 − ySy)2 solar cells, the implementation of a bandgap widening at the absorber/buffer interface via an increase of the [S]/[S + Se] ratio is investigated. In this work we examine industrially processed samples, which were fabricated via the deposition-reaction process with varied H2S pressure during rapid thermal processing (RTP). Precursors which were exposed to a crucial amount of sulfur during the RTP step resulted in samples with significantly improved device performance. The increase of the open circuit voltage by about 150 mV cannot sufficiently be explained by bandgap widening. Observation of a strongly reduced saturation current density and ideality factor in intensively sulfurized samples suggest subdued recombination via mid-gap defect states located in the space charge region. This hypothesis is supported by results of deep-level transient spectroscopy measurements, which show that in both samples a mid-gap minority defect is present albeit its concentration is about one magnitude larger in sulfur-poor samples. These results confirm that sulfur passivates recombination centers in the depletion layer and hence significantly increases the open circuit voltage and the overall device performance of the photovoltaic devices.

Growth of nickel disilicide nanowires by CVD

Abstract A systematic study of the influence of the process parameters on the growth of nickel disilicide (NiSi 2 ) nanowires by CVD (Chemical Vapor Deposition) has been carried out in the temperature range of 350 °C to 550 °C. Ni thin films thinner than 100 nm were dissociated using different RTP (Rapid Thermal Processing) steps in order to create Ni droplets which act as nucleation sites for the nanowire growth. Thereafter, silane (SiH 4 ) was flown over these nucleation sites in an attempt to grown nickel silicide nanowires. The purpose of this report is to determine the optimal set of process parameters promoting the growth of nanowires. Moreover, we have studied the impact of the RTP step and the influence of the original (prior to annealing) thickness and status of the Ni layer that once dissociated acts as a catalyst. Also, the effect of the surface underneath the Ni droplets has been investigated. Scanning Electron Microscopy (SEM) as well as Energy Backscattering Electron Diffraction (EBSD) techniques were used to characterize the as-synthesized nanowires. High-resolution transmission electron microscopy (HR-TEM) results show that the nanowires are monocrystalline with a separation of the lattice planes corresponding NiSi 2 . HR-TEM also showed that the nickel disilicide nanowires do not all grow in a specific growth direction but that several growth directions such as or coexist within one and the same nanowire.

Improved Poly Gate Engineering for 65 nm Low Power CMOS Technology

A design for the polycrystalline gate is developed for low power complementary metal oxide semiconductor (CMOS) technology. Using the poly deposition, a less poly depletion effect and a decrease in the electrical gate dielectric thickness can be obtained. Also, the poly deposition successfully reduces the roughness of the poly surface and produces a smaller poly grain size after subsequent rapid thermal processing steps. Meanwhile, the poly deposition can suppress the short channel effect and can reduce off-state leakage current. The poly deposition results in better voltage ramp dielectric breakdown and uniformity on a specific test vehicle. The asymmetry characteristics of the device are also improved by the poly deposition. The of the cell size 6T-static random access memory using the poly deposition is also improved due to leakage current reduction and well asymmetry.

Benefit of H2 surface pretreatment for 4H-SiC oxynitridation using N2O and rapid thermal processing steps

The effect of H2 surface pretreatment on the density of interface traps in SiO2 films grown on the Si-face of 4H-SiC has been investigated. With respect to the more conventional oxide grown in nitrous oxide gas by rapid thermal processing but without any preannealing step, we find that the interface trap and fixed oxide charge densities have been reduced by, typically, one order of magnitude. The reasons for such improvement in the properties of the SiO2/SiC interface after preoxidation hydrogen annealing are discussed.

Silicides and germanides for nano-CMOS applications

An overview of silicides and germanides for nano-CMOS applications is presented. The historical evolution describing the migration from the use of Ti silicide to Co silicide to Ni silicide as contacting material is first discussed. These changes in silicide material were mainly motivated by the inability to form the target low resistivity silicide phase in small structures due to low nucleation density. This issue was found first for the low resistivity C54 TiSi 2 at linewidths below 200 nm and later for the low resistivity CoSi 2, at linewidths below 40 nm. A detailed description of scalability and thermal stability issues for NiSi is then presented. No nucleation issues were found in small structures for NiSi, which grows by diffusion or interface limited kinetics with Ni as main moving species. However, silicidation can be excessive in small structures due to Ni diffusion from surrounding areas, resulting in thicker films than targeted in small devices. This can be controlled by using a silicidation process with two rapid thermal processing steps, the first one to control the amount of Ni reacted and the second one to convert the silicide to the target low resistivity monosilicide phase. One of the main issues for applications of NiSi is its low thermal stability: thin NiSi films agglomerate at relatively low temperatures. The process window and thermal stability of Ni and Pt-based films reacted with Si, Si:Ge and Si:C substrates is reviewed. Addition of Ge is shown to degrade thermal stability while addition of C or Pt improves it. Contact resistivity considerations and implementation of dual band-edge silicides are discussed, as well as promising results for the extension of Ni-based silicides to future nodes. Finally a brief overview of germanides is presented discussing NiGe and PdGe as main candidates.

Diffraction Originated Local Heating of Nanometer Scale Device Patterns in Lamp-Based Rapid Thermal Annealing

The process results on blanket Si and patterned Si wafers are often very different. Process variations in conventional lamp- based rapid thermal processing (RTP) systems due to pattern size, density and structure dependence under nearly identical process conditions are well known as the pattern effect , but without identifying the root cause. As device dimensions shrink, pattern-induced variability of process results increases which significantly affects the process window, device yield and manufacturability. Understanding the underlying physical causes of the pattern effect is very important to systematically improve device performance, yields and manufacturability. In this paper, the impact of device pattern size and density on process variations in RTP steps was analyzed. According to the analysis, diffraction of light from the periodicity of the nanometer scale device features can result in significant local heating near the critical depths for junctions and contacts.

Structural and electrical characterization of Al 2O 3/HfO 2/Al 2O 3 on strained SiGe

The interfacial integrity of a gate stack featuring a polycrystalline SiGe gate, an ultrathin Al 2O 3/HfO 2/Al 2O 3 nano-laminate and a strained-SiGe surface-channel is examined for full transistor fabrication and characterization. The high-κ dielectric nano-laminate is prepared by means of atomic layer deposition, and the SiGe channel and gate by chemical vapor deposition. After full transistor-processing including a rapid thermal processing step at 930 °C, the 3 nm thick HfO 2 film becomes polycrystalline whereas the Al 2O 3 films about 0.5 nm thick remain in the amorphous state, according to analyses using high-resolution and energy-filtering transmission electron microscopy. No interfacial reaction is observable between the HfO 2 film and the SiGe gate or channel, since both interfaces are flat and the two Al 2O 3 films remain continuous. Well-behaving gate leakage and capacitance characteristics of the transistors are found. An enhanced channel hole mobility compared to the Si universal curve is obtained.

Effects of various Co/TiN and Co/Ti layer stacks and the salicide rapid thermal process conditions on cobalt silicide formation

The effects of cap layer type (Ti or TiN) and its thickness, Co thickness and rapid thermal processing (RTP) temperature on cobalt silicide formation are investigated by a combination of electrical and optical measurements. Various Co/TiN and Co/Ti layer stacks (thicknesses 8–20 nm per layer) were deposited on (100) Si substrates. The first RTP step (RTP1) was performed by isochronal annealing at various temperatures between 400 and 600 °C for 30 s. It was observed that the temperature range for constant sheet resistance (Rs) values after the first RTP step (RTP1 process window) is smaller for the Co/TiN layer stacks than it is for the Co/Ti layer stacks. After the subsequent selective etch step the second RTP step (RTP2) was performed at 800 °C for 30 s. Rs after RTP2 strongly depends on the initial Co thickness and its uniformity for both systems if the RTP1 temperature was above 470 °C. For the Co/TiN layer stacks the final Rs results are not influenced by the RTP1 temperature or its uniformity (above 470 °C). In this case silicidation is independent of the cap thickness. But in the Co/Ti system the reactive Ti influences the silicidation process by reducing the amount of available Co in a manner that depends on the RTP1 temperature and the Ti cap thickness.

Characterization of High-κ Nanolaminates of HfO2 and Al2O3 Used as Gate Dielectrics in pMOSFETs

AbstractIn order to combine the merits of both HfO2 and Al2O3 as high-κ gate dielectrics for CMOS technology, high-κ nanolaminate structures in the form of either Al2O3/HfO2/Al2O3 or Al2O3/HfAlOx/Al2O3 were implemented in pMOSFETs and electrically and microstructurally charachterized. ALD TiN film was used as the metal gate electrodes for the pMOSFETs. After full transistor-processing including a rapid thermal processing step at 930 °C, the HfO2 film in the former nanolaminate was found to be crystallized. In contrast, the HfAlOx layer in the latter nanolaminate remained in the amorphous state. Both types of pMOSFETs exhibited a hysteresis as small as ∼20 mV in C-V characteristics in the bias range of +/− 2 V. They also showed a reduced gate leakage current. The pMOSFET with the Al2O3/HfAlOx/Al2O3 nanolaminate was characterized with a subthreshold slope of 77 mV/decade and a channel hole mobility close to the universal hole mobility curve. The pMOSFET with the Al2O3/HfO2/Al2O3, however, exhibited a subthreshold slope of 100 mV/decade and a ∼30% lower hole mobility than the universal curve.

Record fast thermal processing of 17.5% efficient silicon solar cells

This paper presents the development and analysis of 17.5% efficient silicon solar cells on 0.9 Ω cm PV-grade Czochralski silicon (Cz–Si), featuring a record small thermal process time of 1 min for diffusion and oxidation. The cells have been processed by rapid thermal processing (RTP) using incoherent light as an energy source. The involved processes consist of a 5 s RTP step at 930 °C for the simultaneous formation of the phosphorus-doped emitter and of the aluminium back surface field (Al–BSF) and a 30 s rapid thermal oxidation (RTO) at 950 °C for the emitter surface passivation. Both processes feature high heating and cooling rates of 100 K s−1. The results show that no lengthy gettering or post diffusion annealing steps are required for the fabrication of high efficiency Cz–Si solar cells and that high heating and cooling rates are applicable. Detailed analysis reveals that the emitter saturation current J0e is reduced by a factor of 3–4 after the RTO passivation in spite of the high carrier surface concentrations of 3 to 4 × 1020 cm−3. Furthermore, one-dimensional device simulations are presented which show that the achieved efficiencies are limited by the effective back surface recombination velocity Sback resulting from the thin Al–BSF applied.

SURFACE CHARACTERISTICS OF THICK, FREE-STANDING DIAMOND FILM PREPARED BY CHEMICAL ETCHING AND RAPID THERMAL PROCESSING

The surface characteristics and depth profile of free-standing polycrystalline diamond films chemically etched from silicon substrates have been studied using monochromatic X-ray photoelectron spectroscopy and Auger electron spectroscopy. Two different processes for isolating the diamond films from the silicon substrates have been performed. The isolated/annealed-diamond film was prepared by rapid thermal processing (RTP) of the diamond-on-silicon film at a temperature of 800°C before chemically etching the diamond film from the silicon substrate. The annealed/isolated film was prepared by first chemically etching the diamond film from the silicon substrate, and then subjecting the stand-alone film to RTP. The qualities of the film on the top faces were improved for both the isolated/annealed-diamond and annealed/isolated-diamond films as verified by Raman spectroscopy. XPS analysis revealed different oxidation characteristics on the top and bottom faces of the isolated/annealed-diamond and annealed/isolated-diamond films. Silicon was detected on the bottom surfaces. A higher silicon and oxygen intensity was observed on the isolated/annealed diamond films compared to the annealed/isolated films. This can be due to the facilitated thermal diffusion of silicon into the grain boundaries during the initial RTP step in the preparation of the isolated/annealed-diamond film.

Photoluminescence and X-ray fluorescence measurements of successively thinned CuGaSe2 films

CuGaSe2 thin films were produced by a rapid thermal processing step from evaporated stacked elemental layers of the pure elements. The CuGaSe2 films were analyzed with respect to composition, defect levels and crystallographic phases. To gain insight into the variation of these attributes at different depth, the layers were successively etched in bromine methanol and characterized afterwards. The aim of this work is to investigate the properties of RTP reacted films in general and to disclose influences of the precursor structure on the reacted material.

Fabrication of large area silicon solar cells by rapid thermal processing

Large area n+pp+ solar cells have been fabricated on 10 cm×10 cm pseudo-quasi-square CZ silicon wafers (1 Ω cm, p-type) predominantly used by the photovoltaic (PV) industry. All the high-temperature steps have been performed by rapid thermal processing (RTP). Emitter formation, back surface field (BSF) formation, and surface oxidation have been performed in just two RTP steps each lasting 50 s. Solar cells of 15% efficiency have been fabricated this way, demonstrating the applicability of this low thermal budget technology to large area, modulable size, industrial quality Si wafers. Furthermore, the rapid thermal oxidation (RTO) is shown to result in good quality thin oxides with Si/SiO2 interface trap densities (Dit)<1011 cm−3 eV−1 near-midgap.

Integration of Plasma-Assisted and Rapid Thermal Processing for Low-Thermal Budget Preparation of Ultra-Thin Dielectrics for Stacked-Gate Device Structures

This paper discusses a new approach to the formation of ultra-thin gate dielectrics for Si-ULSI applications in which separately controlled plasma-assisted and/or rapid thermal processing steps are combined to fix the chemical bonding and minimize the defect structure at the Si–SiO2 interface, and within the dielectric layers. One example of this approach combines (i) low-temperature (300° C) plasma-assisted processing to control the initial bonding chemistries at (a) the Si–SiO2 interface, and (b) in homogeneous oxide, or composite dielectrics with nitride or oxynitride layers, with (ii) higher temperature (900° C), but low-thermal budget, rapid thermal annealing to promote physical and/or chemical relaxations that minimize both interfacial and bulk dielectric defects, thereby improving device performance.

Integrated processing of stacked-gate heterostructures: plasma-assisted low temperature processing combined with rapid thermal high-temperature processing

We discuss a novel approach to the formation of deposited stacked-gate structures that combines several different processing steps into a single chamber with multi-function oxidation, passivation and deposition capabilities. To form a Si-based stacked gate structures the following in-situ steps can be performed i) a final cleaning/passivation of the Si surface, ii) formation of the SiO 2/Si interface, iii) deposition of a single, or multi-layer dielectric, e.g., SiO 2, or an oxide/nitride/oxide (ONO) structure, and iv) deposition of a polysilicon gate electrode. We discuss the fabrication and performance of test device structures that combine remote plasma and rapid thermal processing steps, but omit the polysilicon deposition, and use al Al gate electrode instead. These structures are use to demonstrate the effectiveness of different interface formation processes.

Limitations of TiSi2 as a source for dopant diffusion

The application of TiSi2 as a dopant diffusion source for boron and arsenic was studied. The TiSi2 layers were formed by the usual salicide process and doped by ion implantation. Diffusion was carried out by various furnace and rapid thermal processing steps. Using secondary ion mass spectrometry, scanning electron microscopy, and x-ray diffraction, clear evidence for compound formation between Ti and the two dopant species is found. This leads to low dopant concentrations at the silicide/silicon interface, very poor efficiency of the diffusion source, and unacceptably high contact resistivities.

Limited reaction processing: In-situ metal—oxide—semiconductor capacitors

Limited reaction processing (LRP) has been used to fabricate in-situ silicon-silicon dioxide-polycrystalline silicon layers for metal-oxide-semiconductor (MOS) capacitors. The process consists of multiple in-situ rapid thermal processing steps to grow or deposit different layers. Capacitors have been fabricated from these layers and analyzed by capacitance-voltage measurements for interfacial fixed charge and interface state density. The capacitors exhibit excellent characteristics.