Integrated processing of stacked-gate heterostructures: plasma-assisted low temperature processing combined with rapid thermal high-temperature processing

Abstract

We discuss a novel approach to the formation of deposited stacked-gate structures that combines several different processing steps into a single chamber with multi-function oxidation, passivation and deposition capabilities. To form a Si-based stacked gate structures the following in-situ steps can be performed i) a final cleaning/passivation of the Si surface, ii) formation of the SiO 2/Si interface, iii) deposition of a single, or multi-layer dielectric, e.g., SiO 2, or an oxide/nitride/oxide (ONO) structure, and iv) deposition of a polysilicon gate electrode. We discuss the fabrication and performance of test device structures that combine remote plasma and rapid thermal processing steps, but omit the polysilicon deposition, and use al Al gate electrode instead. These structures are use to demonstrate the effectiveness of different interface formation processes.