Supply Voltage Range Research Articles

Hardware Implementation of Overvoltage and Under voltage Protection

2,3 Abstract: The aim of the project is to make a low voltage and high voltage indicator. The system will save costly electrical and electronic appliances from the adverse effects of very high and very low mains voltages. A project has been proposed on simulating a overvoltage and under-voltage protector, with the hardware. The advantages of our project are -Wide single supply voltage range 2.0 V DC to 36 V DC ,Very low supply current drain (0.8mA) independent of supply voltage , low input biasing current 25mA.,Input common mode voltage range includes ground, differential input voltage range equal to the power supply voltage.

A switch‐utilization‐improved switched‐inductor switched‐capacitor converter with adapting stage number

SUMMARYA novel closed‐loop switched‐inductor switched‐capacitor converter (SISCC) is proposed by using the pulse‐width‐modulation (PWM) compensation for the step‐up DC–DC conversion/regulation, and together by combining the adaptive‐stage‐number (ASN), control for the higher switch utilization and wider supply voltage range. The power part of SISCC is composed of two cascaded sub‐circuits, including (i) a serial‐parallel switched‐capacitor circuit withncpumping capacitors and (ii) a switched‐inductor booster withmcresonant capacitors, so as to obtain the high step‐up gain of (nc + 1) × mc /(1 − D) at most, whereDis the duty cycle of PWM adopted to enhance output regulation as well as robustness to source/loading variation. Besides, the ASN control is presented with adapting the stage numbern(n = 0, 1, 2, …, nc) of pumping capacitors to obtain a flexible gain of (n + 1) × mc /(1 − D), and further in order to make the SISCC operating at a properly small duty cycle for improving switch utilization and/or supply voltage range. Some theoretical analysis and control design include formulation, steady‐state analysis, ASN‐based conversion ratio, efficiency, output ripple, stability, inductance and capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on an ASN‐based SISCC prototype, and all results are illustrated to show the efficacy of this scheme. Copyright © 2015 John Wiley & Sons, Ltd.

Micropower Clock Generator Circuit Using an Optimized Band-Gap Reference for Energy Harvesting Charge Pumps

In recent years, a lot of research and effort have been developed in micro-scale energy harvesting (EHV) for Wireless Sensor Networks (WSN) because of their viable and promising approach for self powering low voltage circuit. The key element in such an application is the charge pump circuit as a power converter. A charge pump (CP) driven by tow pumping clocks, is introduced to generate voltages beyond the supply voltage range. In this paper, a clock circuit for a charge pump was proposed. This circuit was achieved using tow components: a Voltage Control Ring Oscillator (VCOR) as a clock generator and a Band-Gap Reference (BGR) as a voltage reference. The circuit was implemented using 0.35 µm CMOS process, and was generated the desired pumping clocks signals at tens of Mhz under just 9.6 µW for a power supply of only 1V.

Ratioless full-complementary 12-transistor static random access memory for ultra low supply voltage operation

In this study, a ratioless full-complementary 12-transistor static random access memory (SRAM) was developed and measured to evaluate its operation under an ultra low supply voltage range. The ratioless SRAM design concept enables a memory cell design that is free from the consideration of the static noise margin (SNM). Furthermore, it enables a SRAM function without the restriction of transistor parameter (W/L) settings and the dependence on the variability of device characteristics. The test chips that include both conventional 6-transistor SRAM cells and the ratioless full-complementary 12-transistor SRAM cells were developed by a 180 nm CMOS process to compare their stable operations under an ultralow supply voltage condition. The measured results show that the ratioless full-complementary 12-transistor SRAM has superior immunity to device variability, and its inherent operating ability at the supply voltage of 0.22 V was experimentally confirmed.

Magnetic Random Access Memory based non-volatile asynchronous Muller cell for ultra-low power autonomous applications

Micro and nano electronic integrated circuit domain is today mainly driven by the advent of the Internet of Things for which the constraints are strong, especially in terms of power consumption and autonomy, not only during the computing phases but also during the standby or idle phases. In such ultra-low power applications, the circuit has to meet new constraints mainly linked to its changing energetic environment: long idle phases, automatic wake up, data back-up when the circuit is sporadically turned off, and ultra-low voltage power supply operation. Such circuits have to be completely autonomous regarding their unstable environment, while remaining in an optimum energetic configuration. Therefore, we propose in this paper the first MRAM-based non-volatile asynchronous Muller cell. This cell has been simulated and characterized in a very advanced 28 nm CMOS fully depleted silicon-on-insulator technology, presenting good power performance results due to an extremely efficient body biasing control together with ultra-wide supply voltage range from 160 mV up to 920 mV. The leakage current can be reduced to 154 pA thanks to reverse body biasing. We also propose an efficient standard CMOS bulk version of this cell in order to be compatible with different fabrication processes.

A BL-CSC Converter-Fed BLDC Motor Drive With Power Factor Correction

This paper presents a power factor correction (PFC)-based bridgeless canonical switching cell (BL-CSC) converter-fed brushless dc (BLDC) motor drive. The proposed BL-CSC converter operating in a discontinuous inductor current mode is used to achieve a unity power factor at the ac mains using a single voltage sensor. The speed of the BLDC motor is controlled by varying the dc bus voltage of the voltage source inverter (VSI) feeding the BLDC motor via a PFC converter. Therefore, the BLDC motor is electronically commutated such that the VSI operates in fundamental frequency switching for reduced switching losses. Moreover, the bridgeless configuration of the CSC converter offers low conduction losses due to partial elimination of diode bridge rectifier at the front end. The proposed configuration shows a considerable increase in efficiency as compared with the conventional scheme. The performance of the proposed drive is validated through experimental results obtained on a developed prototype. Improved power quality is achieved at the ac mains for a wide range of control speeds and supply voltages. The obtained power quality indices are within the acceptable limits of IEC 61000-3-2.

Automating the sizing of transistors in CMOS gates for low‐power and high‐noise margin operation

SummaryThis paper presents an automatic method for sizing the transistors in CMOS gates. The method utilizes a feedback control system to efficiently optimize the transistor sizes in small and large fan‐in gates, with the primary goal of enhancing noise robustness (as characterized by the static noise margin). The gates retain their robustness under threshold‐voltage variations over a range of supply voltages. The optimized gates not only expend reduced power and energy, but also take up less area than the conventional ones. These multi‐faceted gains, however, do incur some performance loss. Copyright © 2014 John Wiley & Sons, Ltd.

A Reconfigurable 40-to-67 dB SNR, 50-to-6400 Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels

This paper describes a capacitive touch-screen panel (TSP) readout IC that provides a reconfigurable SNR and frame rate with high noise immunity and touch sensitivity. The readout IC mitigates severe noise interference with a lock-in sensing architecture. In addition, a band-pass filtering effect by the TSP and charge amplifier further improves the noise immunity. A differential sensing scheme is employed to enhance the touch sensitivity and to reject a common-mode noise. A column-parallel incremental ΣΔ ADC is adopted to provide a high resolution and frame rate. Furthermore, a multiple sampling and averaging effect of the ADC enhances the noise immunity. The readout IC reconfigures its SNR and frame rate by adjusting the configurable resolution of the employed ADC. The test chip is fabricated in a 0.18 μm CMOS process and occupies a 2.2 mm 2 active area. The test chip achieves a 60 dB SNR and 200 Hz frame rate with a 12×8 TSP. The SNR can be adjusted from 40 dB to 67 dB, while the frame rate is then inversely scaled from 50 Hz to 6.4 kHz. The test chip supports a supply voltage range from 2.1 V to 3.3 V and consumes 6.26 mW from a 3.3 V supply.

One Kind of Band-Gap Voltage Reference Source with Piecewise High-Order Temperature Compensation and Power Supply Rejection Ratio

This paper designed a new band-gap voltage reference circuit with two-stage temperature compensation.It realizes non-linear temperature compensation by using NMOS-pipe leakage current and increases the power supply rejection ratio of the band-gap voltage reference source by introducing negative feedback between the operational amplifier and the power supply. What is more, the paper simulates the band-gap voltage reference source based on CSMC 0.5μm CMOS technique. The result as follow: the band-gap voltage reference source has the temperature coefficient of 8.2ppm/oC among-40-120oC with the supply voltage of 3V, the low-frequency power supply rejection ratio is 83dBat 27oC and the power supply rejection ratio is 71dB in 1KHz, the output voltage regulation is 1.05mV/V in the supply voltage range from 2.4V to 5V.

An Area-Efficient 96.5%-Peak-Efficiency Cross-Coupled Voltage Doubler With Minimum Supply of 0.8 V

An area-efficient cross-coupled voltage doubler (CCVD) with no reversion loss using first-level gate-control mechanism is presented. The proposed design does not require area-consuming resistors or extra power MOSFETs to prevent reversion currents. Through the first-level gate controls, the proposed CCVD is able to use internal nodes to drive the gates of the power MOSFETs without extra buffers, thus further reducing the silicon area and power consumption. The proposed design has been fabricated in a commercial 0.35-μm CMOS technology (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">THN</sub> ≈ 0.59 V, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">THP</sub> ≈ -0.72 V), with an active area of only 0.49 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Experimental results show that it can achieve a maximum of 96.5% power efficiency value under a supply voltage range of 0.8-1.6 V with a maximum loading current of 30 mA.

함정 자기신호 측정용 3-축 디지털 자기센서 설계 및 제작에 관한 연구

Dept. of Photonics and Sensors, Hannam University, Daejeon 306-791, Korea(Received 26 July 2014, Received in final form 18 August 2014, Accepted 18 August 2014)We developed a digital 3-axis flux-gate magnetometer for magnetic field signal measurement from warship during demagnetizingand degaussing processes. For the magnetometer design, we considered following points; the distance between magnetic fieldmeasurement station and magnetometer located under sea is about several 100 m, the magnetometer is exposed to magnetic field of± 1 mT during demagnetizing process, and magnetometer is located under the sea about 30 m depth. To overcome long distanceproblem, magnetometer could be operated on wide input supply voltage range of 16~36 V using DC/DC converter, and for the datacommunication between the magnetometer and measurement station a RS422 serial interface was employed. To improve permingeffect due to the ± 1 mT during demagnetizing process, magnetometer could be compensated external magnetic field up to ± 1 mT butmagnetic field measuring rang is only ± 100µT. The perming effect was about ± 2 nT under ± 1 mT external magnetic field. Themagnetometer was tested water vessel with air pressure up to 6 bar for the sea water pressure problems. Linearity of the magnetometerwas better than 0.01 % in the measuring range of ± 0.1 mT and noise level was 30 pT/ at 1 Hz.Keywords: Magnetometer, flux-gate magnetometer, low magnetic field, perming, amorphous core

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

Gain cells have recently been shown to be a viable alternative to static random access memory in low-power applications due to their low leakage currents and high density. The primary component of power consumption in these arrays is the dynamic power consumed during periodic refresh operations. Refresh timing is traditionally set according to a worst-case evaluation of retention time under extreme process variations, and worst-case access statistics, leading to frequent power-hungry refresh cycles. In this brief we present a replica technique for automatically tracking the retention time of a gain-cell-embedded dynamic-random-access-memory macrocell according to process variations and operating statistics, thereby reducing the data retention power of the array. A 2-kb array was designed and fabricated in a mature 0.18-μm CMOS process, appropriate for integration in ultralow power applications, such as biomedical sensors. Measurements show efficient retention time tracking across a range of supply voltages and access statistics, lowering the refresh frequency by more than 5×, as compared with traditional worst-case design.

Requirements and Difficult Challenges for Packaging in the Era of “More Than Moore”

The benefits of Moore’s Law are slowing as we reach the limits of scaling imposed by the laws of physics. The advantages of higher speed and lower power requirements no longer scale with device feature size. One approach to increase functional density as the benefits of scaling slow is to incorporate functional diversification within a single package. Combining analog, RF, power devices, optical devices, MEMS and other devices types into a single package enables this functional diversification. System-in-package (SiP) architectures combining these components with logic and memory that follow Moore’s Law offsetting much of the decreased benefits of scaling has been called “More than Moore”.This sounds very simple but there are many difficult challenges that arise in incorporating components with diverse requirements into a single, high density package and delivering the reliable performance demanded by the markets. These challenges include: Lack of adequate modeling and simulation tools for complex SiP packagesThermal management with increased thermal density, “hot spots”, etc.Stress and warpage associated with CTE differences between various componentsCross talk between componentsProtecting fragile components such as thinned die, MEMS and compound semiconductorsMaintaining power integrity with widely varying power requirements of various componentsRequirements for both hermitic and open packages for sensor environmental access There are many other challenges as we increase the density of components and interconnect wiring, incorporate heterogeneous integration of both component types and materials used, support a wide range of supply voltages from below 400mV to several volts and incorporate 3D integration. Perhaps the most difficult challenge is to meet these expanding requirements while continuously driving down the cost per function demanded by the markets. Traditionally, packaging has not scaled down in cost with shrinking geometries as quickly as CMOS integrated circuits. Introduction of complex “More than Moore” SiP packages makes this cost challenge much more difficult.The ITRS was established to forecast the difficult challenges that must be met to satisfy future requirements with sufficient lead time to allow implement a solution. This process has been very successful and, since the beginning of the ITRS, packaging challenges have not prevented continued end user product cost reduction and performance increases. The packaging solutions needed now to continue these improvements in size, cost and performance cannot be delivered by continuing down a known path as we did with CMOS scaled integrated circuits. Everything has to change.This includes package architectures, design and simulation tools, materials, connections, etc. Many of these changes are underway but there is much more to come. Specific examples of requirements, challenges and potential solutions for packaging in the Era of ‘More than Moore” identified in the 2013 ITRS will be discussed.

Performance and breakdown behavior of graphene field-effect transistors with thin gate oxides

Reactive ion etching is employed to fabricate graphene field-effect transistors (GFETs) with different thicknesses of SiO2 dielectric. The output characteristic of the GFETs with 10 nm gate oxide demonstrates that the gate supply voltage range is from −3.5 to 3.5 V, which is suitable for use in MEMS/NEMS devices, while the supply voltage range of the GFET with 300 nm SiO2 is from −100 to 100 V. The GFET with 10 nm SiO2 reduces the gate supply voltage and the performance is similar to GFET with 300 nm SiO2. The position of the Dirac point depends on several factors, but the surfactant on SiO2 may be the main one. Reliability of thin oxides in GFETs is an important concern. After the time-zero dielectric breakdown of 10 nm SiO2, there is an electric current flowing though the graphene sheet when drain voltage is not applied to the device. This phenomenon may be attributed to the Schottky-like diode of graphene/10 nm SiO2/silicon interfaces. This study also provides a method to identify whether the graphene transistor is damaged or not.

Tunnel FET technology: A reliability perspective

Tunneling-field-effect-transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage (VDD) scaling in ultra-low power, energy efficient computing, due to its sub-60mV/decade sub-threshold slope (SS). Given its unique device characteristics such as the asymmetrical source/drain design induced uni-directional conduction, enhanced on-state Miller capacitance effect and steep switching at low voltages, TFET based circuit design requires strong interactions between the device-level and the circuit-level to explore the performance benefits, with certain modifications of the conventional CMOS circuits to achieve the functionality and optimal energy efficiency. Because TFET operates at low supply voltage range (VDD<0.5V) to outperform CMOS, reliability issues can have profound impact on the circuit design from the practical application perspective. In this review paper, we present recent development on Tunnel FET device design, and modeling technique for circuit implementation and performance benchmarking. We focus on the reliability issues such as soft-error, electrical noise and process variation, and their impact on TFET based circuit performance compared to sub-threshold CMOS. Analytical models of electrical noise and process variation are also discussed for circuit-level simulation.

Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple-Cell Upsets in 10T Subthreshold SRAM

This paper presents measurement results of alpha-particle-induced soft errors and multiple-cell upsets (MCUs) in 65-nm 10T SRAM with a wide range of supply voltage from 1.0 to 0.3 V. We reveal that the soft-error rate (SER) at 0.3 V is six times higher than that at 1.0 V and the MCU rate significantly increases in the subthreshold region. To investigate the reason for the MCU increase, the dependences of the MCU rate on the body-bias voltage and the distance between well ties are examined, and we conclude that the main cause of the MCU increase is not the parasitic bipolar effect but another mechanism, such as charge sharing. In addition, the dependence of the variation in the soft-error immunity of each memory cell on the supply voltage is examined, since SRAMs operating in the subthreshold region are sensitive to manufacturing variability. Measurement results indicate that the number of soft errors in each memory cell varies cell by cell, whereas the cause of the variation is explained by the spatial randomness of alpha-particle hits, and a distinct influence of manufacturing variability is not observed even in the subthreshold region.

Modeling of High Performance 4H-SiC Emitter Coupled Logic Circuits

SiC, a wide band gap semiconductor, is capable of robust operation at temperatures well above 600°C. SiC bipolar transistors are well suited for applications at high temperatures as, unlike MOSFET, it does not have a critical gate oxide, and hence oxide reliability at high temperatures is not an issue. In this paper, the design of optimized emitter coupled logic technology circuits using 4H-SiC bipolar transistors is presented. The circuits work over a wide range of temperatures and power supply voltages at high speeds, demonstrating the potential of robust high speed ECL integrated circuits in SiC for small-scale logic applications.

A Novel High Performance Low Power Universal Gate Implementation in Subthreshold Region

any integrated circuit power consumption plays a paramount role and is considered as one of the top challenges in International technology roadmap for semiconductors. In this paper, a low power circuit designed to operate in subthreshold region is proposed. Voltage scaling technique is incorporated to reduce dynamic power consumption while static or leakage power is greatly reduced with forced stack technique. The present technique (VS-STACK) features very low power dissipation as compared to its standard CMOS counterparts in subthreshold region. The power consumption is curtailed by 20% to 90% together with a better power delay product (PDP) over a supply voltage range. The technique is tested on a 2-input NOR gate in the 45nm process. Tanner Tool EDA 13.0v is used for simulation.

Minimal power start-up circuit design for self-biased CMOS current generators

A new start-up circuit configuration, with minimal standby power dissipation, is proposed for CMOS self-biased current generators. Using standard 0.13 µm CMOS technology, simulation results show that for a supply voltage range 1.8 V to 2.5 V and a temperature range −40°C to +85°C, the circuit standby power dissipation is less than 20 nW.

A low power low supply sensitivity current-mode relaxation oscillator

This paper presents a design of a 100 kHz 0.54 µW fully integrated current-mode relaxation oscillator. The transistors in the sub-threshold region, the current-mode comparator, the current-starving RS flip-flop are used to reduce the power consumption. Meanwhile, the employing of the current-starving RS flip-flop significantly reduces the sensitivity of the frequency to supply voltage fluctuation. The temperature coefficient is 51 ppm/°C from −40 to 85 °C, and the line regulation is −0.40%/V over a supply voltage range from 1.0 to 2.0 V. This oscillator is designed in SMIC 0.18 µm CMOS technology and operates at minimum supply voltage of 1.0 V with drawn current of 540 nA at room temperature.