Random Telegraph Noise Effects Research Articles

The Drain Bias Modulation Effect of Random Telegraph Noise in Gate-All-Around FETs for Cryogenic Applications

The Drain Bias Modulation Effect of Random Telegraph Noise in Gate-All-Around FETs for Cryogenic Applications

Low-temperature enhanced OFF-state telegraph noise in defect engineered ReRAMs

The OFF-state retention characteristics of Pt/NiOx–(Ar)/NiOx–(Ar + O2)/Pt stacking resistive random access memory structures were measured as a function of temperature between 300 and 190 K. The devices show random telegraph noise effects whose noise amplitude increases upon lowering the temperature. Interestingly, the application of forward and reverse biases produces up and downresistance jumps. These results present important insights into the thermally activated charge trapping/de-trapping phenomenon that is responsible for resistance fluctuations.

Random Telegraph Noise and Bias Temperature Instabilities statistical characterization of Ω-gate FDSOI devices at low voltages

Random Telegraph Noise (RTN) and Bias Temperature Instabilities (BTI) are two mechanisms that can significantly reduce the performance and reliability of integrated circuits. In scaled devices, both phenomena are stochastic, so that a statistical analysis is required to accurately evaluate their impact on a particular technology. This study presents such analysis in scaled FD-SOI devices under various gate and drain voltages, ranging from near-threshold to nominal conditions. The combined effect of RTN and BTI is also modeled in a defect-centric context, and the main impact of the different bias conditions is discussed.

Random Telegraph Noise in Analog CMOS Circuits

Flicker noise, or 1/f noise, is known to increase as devices scale down. However, as the scaling of MOS transistors advances, the effect of individual oxide defects, which originates flicker noise, becomes apparent through distinguishable discrete fluctuation in current. In such cases, flicker noise is recognizable as random telegraph noise (RTN). Another typical characteristic of RTN is that seemingly identical devices have different noise characteristics, as RTN variability from device to device also increases with scaling. Due to the large variability of RTN in highly-scaled devices, circuit yield must be evaluated during noise analysis. This work proposes a model to analyze the effect of RTN in analog circuits and to evaluate circuit yield. The model can be used in the traditional workflow of noise analysis. The model estimates the distribution of RTN power from the distribution of the noise spectral density. Then, quantiles from the power distribution are used for predicting current/voltage fluctuations for a given yield. This work shows how to use the proposed model to calculate random decision errors in comparators, jitter in oscillators and phase-locked loops, and the impact of RTN in correlated double sampling circuits.

Advanced Data Encryption ​using 2D Materials.

Advanced data encryption requires the use of true random number generators (TRNGs) to produce unpredictable sequences of bits. TRNG circuits with high degree of randomness and low power consumption may be fabricated by using the random telegraph noise (RTN) current signals produced by polarized metal/insulator/metal (MIM) devices as entropy source. However, the RTN signals produced by MIM devices made of traditional insulators, i.e., transition metal oxides like HfO2 and Al2 O3 , are not stable enough due to the formation and lateral expansion of defect clusters, resulting in undesired current fluctuations and the disappearance of the RTN effect. Here, the fabrication of highly stable TRNG circuits with low power consumption, high degree of randomness (even for a long string of 224 - 1 bits), and high throughput of 1 Mbit s-1 by using MIM devices made of multilayer hexagonal boron nitride (h-BN) is shown. Their application is also demonstrated to produce one-time passwords, which is ideal for the internet-of-everything. The superior stability of the h-BN-based TRNG is related to the presence of few-atoms-wide defects embedded within the layered and crystalline structure of the h-BN stack, which produces a confinement effect that avoids their lateral expansion and results in stable operation.

Sustained charge-echo entanglement in a two charge qubits under random telegraph noise

The echo signal influence in restoring the coherence lost due to a random telegraph noise (RTN) in a double quantum dot has been theoretically investigated. In this paper, we discuss the RTN effects according to two different protocols manipulations: free induction and echo signal. The time evolution of the coherence factor for both protocols is evaluated employing the equation of motion approach. The time dependence of both fidelity and purity is numerically assessed as well. Our results unveil an enhancement in the entangled states lifetime and how the effects of the RTN, ubiquitous to the solid-state devises, can be counteracted. Furthermore, applying charge-echo stretches the coherence time. Our results exhibit an improvement by 4 times of the coherence time, proving the echo signal efficiency. It is worth mentioning that our analysis is also applicable to other solid-state devices and helpful for further understanding the open quantum systems dynamics.

SRAM Stability Analysis and Performance–Reliability Tradeoff for Different Cache Configurations

Bias temperature instability (BTI), hot carrier injection (HCI), gate-oxide time-dependent dielectric breakdown (GTDDB), and random telegraph noise (RTN) degrade the stability of the deeply scaled transistors and the overall circuit reliability. These front-end wearout mechanisms are especially acute in the static random access memory (SRAM) cells of first-level (L1) caches, which are crucial for the performance of microprocessors due to frequent accesses. This article presents a methodology to analyze cache reliability degradation due to the combined effect of BTI, HCI, GTDDB, and RTN for different cache configurations, including variations due to associativity, cache line size, cache size, and the error-correcting codes (ECCs). Time-zero variability due to process and environmental parameters are also considered. First, we analyze how each wearout mechanism affects reliability degradation. Then we analyze the relationship between reliability (probability of failure) and performance (hit rate) of the L1 cache within a LEON3 microprocessor, while the LEON3 is running a set of benchmarks, which determine cell array activity, characterized by the duty cycle, toggle rate, temperature, and supply voltage distributions of cells. Insights on the performance-reliability tradeoff are provided for cache designers.

Microcontroller TRNGs Using Perturbed States of NOR Flash Memory Cells

This paper introduces a new technique that perturbs split-gate NOR Flash memory cells and extracts randomness of read noise to generate true random numbers. Flash memory cells exhibit threshold voltage fluctuations during read operations caused by thermal noise and random telegraph noise effects. Recent proposals demonstrate how these inherent properties of Flash memory cells can be used to create true random numbers in modern NAND Flash memories. However, they cannot be directly applied to NOR Flash memories in microcontrollers that have different architecture, improved data retention, high endurance, and are not as susceptible to noise as high-density NAND Flash memories. The proposed technique is experimentally demonstrated and evaluated using a family of commercial microcontrollers. The evaluation shows that it enables extraction of high-throughput random sequences that pass the NIST statistical tests. Advantages of the proposed technique are as follows: (a) it does not require any special hardware and/or interface modifications, (b) it is robust, cost-effective, and high-throughput, (c) it is entirely implemented in software, and (d) it is flexible and can be tailored to work in low-end microcontrollers that are often resource- or cost-constrained.

Qubit systems subject to unbalanced random telegraph noise: quantum correlations, non-Markovianity and teleportation

We address the dynamics of quantum correlations in a two-qubit system subject to unbalanced random telegraph noise (RTN) and discuss in details the similarities and the differences with the balanced case. We also evaluate quantum non-Markovianity of the dynamical map. Finally, we discuss the effects of unbalanced RTN on teleportation, showing that noise imbalance mitigates decoherence and preserves teleportation fidelity.

CSRO-Based Reconfigurable True Random Number Generator Using RRAM

In this paper, we propose a high-speed (kilohertz–megahertz), reconfigurable current starved ring oscillator (CSRO)-based true random number generator (TRNG) design. The proposed TRNG exploits the intradevice stochastic variations in resistive RAM switching parameters and random telegraph noise (RTN). We demonstrate the effect of RTN on the jitter of CSRO oscillations. We also propose a methodology to reconfigure the TRNG to generate new random numbers. The proposed 10-bit TRNG is validated by NIST test suite for randomness in the data stream. Energy/bit is 22.8 fJ for generation, and the speed of random data generation is 6 MHz. Security vulnerabilities and countermeasures of the proposed TRNG are also investigated.

Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV

Near-threshold computing (NTC) poses stringent constraints on designing reliable circuits, as degradations have a magnified impact at lower supply voltages ( $V_{\text {dd}}$ ) compared with super-threshold supply voltages. While phenomena, such as bias temperature instability (BTI) scale down with $V_{\text {dd}}$ , mitigate their magnified impact with reduced degradations and, thus, have little impact on NTC reliability. Process variation (PV) and random telegraph noise (RTN) do not scale with $V_{\text {dd}}$ and, therefore, become key reliability challenges in NTC. On the other hand, in super-threshold computing (STC), PV and BTI are the dominant phenomena, as BTI induces considerable degradations at nominal $V_{\text {dd}}$ and PV imposes large enough shifts to matter at any supply voltage. Therefore, to allow $V_{\text {dd}}$ -scaling from super-to near-threshold, we need to consider all of BTI, RTN, and PV. Ergo, we present a unified RTN and BTI model that models their shared physical origin and is validated against experimental data across a wide voltage range. Our unified model and PV model capture the joint impact of RTN, BTI, and PV within a probabilistic reliability estimation for NTC and STC circuits. We employed our proposed model to analyze the reliability of SRAM cells showing how taking error correction codes into account is able to mitigate the deleterious effects of BTI, RTN, and PV by 36% compared with unprotected circuits.

Bipolar Resistive RAM Based on <formula formulatype="inline"> <tex Notation="TeX">${\rm HfO}_{2}$</tex> </formula>: Physics, Compact Modeling, and Variability Control

In this paper, we thoroughly investigate the characteristics of the ${\rm TiN/Ti/HfO}_{2}/{\rm TiN}$ resistive random access memory (RRAM) device. The physical mechanisms involved in the device operations are comprehensively explored from the atomistic standpoint. Self-consistent physics simulations based on a multi-scale approach are employed to achieve a complete understanding of the device physics. The latter includes different charge and ion transport phenomena, as well as structural modifications occurring during the device operations. The main sources of variability are also included by connecting the electrical response of the device to the atomistic material properties. The detailed understanding of the device physics allows developing a physics-based compact model describing the device switching in different operating conditions, including also the effects of cycling variability. Random telegraph noise (RTN), which constitutes an additional variability source, and its relations with cycling variability are analyzed. A statistical link between the programmed resistance and the worst-case RTN effect is found and exploited to include RTN effects in the compact model. Finally, we show how implementing an advanced programming scheme tailored on the device physics allows optimal control over variability and RTN, eventually achieving reliable and RTN-resilient two-bits/cell operations.

Impacts of Random Telegraph Noise (RTN) on Digital Circuits

Random telegraph noise (RTN) is one of the important dynamic variation sources in ultrascaled MOSFETs. In this paper, the recently focused ac trap effects of RTN in digital circuits and their impacts on circuit performance are systematically investigated. Instead of trap occupancy probability under dc bias condition (p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> ), which is traditionally used for RTN characterization, ac trap occupancy probability (p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ac</sub> ), i.e., the effective percentage of time trap being occupied under ac bias condition, is proposed and evaluated analytically to investigate the dynamic trapping/detrapping behavior of RTN. A simulation approach that fully integrates the dynamic properties of ac trap effects is presented for accurate simulation of RTN in digital circuits. The impacts of RTN on digital circuit performances, e.g., failure probabilities of SRAM cells and jitters of ring oscillators, are then evaluated by the simulations and verified against predictions based on p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ac</sub> . The results show that degradations are highly workload dependent and that p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ac</sub> is critical in accurately evaluating the RTN-induced performance degradation and variability. The results are helpful for robust and resilient circuit design.

Circuit simulation of workload-dependent RTN and BTI based on trap kinetics

A simulation methodology is presented capable of evaluating the transient impact of trap kinetics in transistors at the circuit level and thus the effects caused by them, particularly Random Telegraph Noise (RTN) and Bias Temperature Instability (BTI). The downscaling of channel area leads to transistors with a smaller number of traps, but each trap causing a larger impact on the transistor’s electrical parameters, increasing its importance in circuit reliability. Despite the increasing impact of these effects on circuit reliability there are still no Computer-Aided Design (CAD) tools capable of analyzing the trapping kinetics and the methodologies presented in the literature suffer from either lack of computational efficiency or accuracy. This paper presents a comprehensive trap simulation methodology relying on both theoretical evaluations and experimental device characterization. The developed simulation framework performs a transient SPICE simulation on an arbitrary design considering the trap activity in situ, allowing accurate simulations of both RTN and BTI effects, at DC, AC or arbitrarily changing bias conditions. In order to perform statistical simulations, the simulation framework may be run inside a Monte Carlo loop. Case studies on a SRAM and on a ring oscillator are performed considering the workload dependence and the BTI effect during the simulation.

An RTN Variation Tolerant SRAM Screening Test Design with Gaussian Mixtures Approximations of Long-Tail Distributions

This paper points out that the ordinary screening-test design (STD) will be no longer available when once the random telegraph noise (RTN) could not be ignored any more, resulting from a significantly increasing of the time-dependent modulation of the overall voltage-margin variations (OVMV). Since the major RTN effect on the OVMV modulation comes up after the screening, the actual precision of the STD must rely entirely upon the estimation accuracy of the RTN effect. The proposed STD is based on the developed statistical convolution model capable of fulfilling the following requirements: (1) precisely approximating the non Gaussian tail distribution of the RTN by simple Gaussian mixtures model (GMM), (2) accurately convoluting the RTN tail with the distribution of the Gaussian random dopant fluctuation (RDF). The proposed concepts are 1) sequentially and adaptively segmentation of the long tailed distributions such that the log-likelihood of the GMM in each segment is maximized. It has been verified that the proposed method can reduce the error of the fail-bit predictions by 3-orders of magnitude at the interest raw score where the fail probability pdf = 10−12 which corresponds to a 99.9 % yield for 1Gbit chips.

Impact of Random Telegraph Noise Profiles on Drain-Current Fluctuation During Dynamic Gate Bias

The influence of random telegraph noise (RTN) in MOSFETs on drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ) during the rise/fall edges of the pulsed gate voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) cycle was investigated. We have revealed for the first time that the existence of RTN increases I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> fluctuations under dynamic V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> by making a comparison between FETs with and without RTN. The initial trap occupation states before varying V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> , which are governed by the RTN profiles, significantly affect the Id values during the rise/fall edges of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> . The revealed effects of RTN with different profiles on I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> under dynamic V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> will be useful for designing ultrahigh speed circuits.

Random telegraph noise and resistance switching analysis of oxide based resistive memory

Resistive random access memory (RRAM) devices (e.g."memristors") are widely believed to be a promising candidate for future memory and logic applications. Although excellent performance has been reported, the nature of resistance switching is still under extensive debate. In this study, we perform systematic investigation of the resistance switching mechanism in a TaOx based RRAM through detailed noise analysis, and show that the resistance switching from high-resistance to low-resistance is accompanied by a semiconductor-to-metal transition mediated by the accumulation of oxygen-vacancies in the conduction path. Specifically, pronounced random-telegraph noise (RTN) with values up to 25% was observed in the device high-resistance state (HRS) but not in the low-resistance state (LRS). Through time-domain and temperature dependent analysis, we show that the RTN effect shares the same origin as the resistive switching effects, and both can be traced to the (re)distribution of oxygen vacancies (VOs). From noise and transport analysis we further obtained the density of states and average distance of the VOs at different resistance states, and developed a unified model to explain the conduction in both the HRS and the LRS and account for the resistance switching effects in these devices. Significantly, it was found that even though the conduction channel area is larger in the HRS, during resistive switching a localized region gains significantly higher VO and dominates the conduction process. These findings reveal the complex dynamics involved during resistive switching and will help guide continued optimization in the design and operation of this important emerging device class.

Accurate Prediction of Random Telegraph Noise Effects in SRAMs and DRAMs

With aggressive technology scaling and heightened variability, circuits such as SRAMs and DRAMs have become vulnerable to random telegraph noise (RTN). The bias dependence (i.e., non-stationarity), bi-directional coupling, and high inter-device variability of RTN present significant challenges to understanding its circuit-level effects. In this paper, we present two computer-aided design (CAD) tools, SAMURAI and MUSTARD, for accurately estimating the impact of non-stationary RTN on SRAMs and DRAMs. While traditional (stationary) analysis is often overly pessimistic (e.g., it overestimates RTN-induced SRAM failure rates), the predictions made by SAMURAI and MUSTARD are more reliable by virtue of non-stationary analysis.

Compact modeling and simulation of Random Telegraph Noise under non-stationary conditions in the presence of random dopants

A new methodology for circuit level transient simulation of Random Telegraph Noise (RTN) is proposed. The physically based methodology properly models the microscopic phenomena involved in RTN, including their stochastic nature. Using a modified BSIM code, the compact model is implemented in a SPICE simulator, accounting for non-stationary RTN effects under arbitrary bias. The probability of traps to capture or emit charge carriers is updated at each time step of the transient simulation according to the actual bias conditions of the device. Atomistic device simulations are performed in order to study the impact of trap position along the channel on the amplitude of the contribution of a trap to RTN. These device simulations take into account short-range Coulomb interactions and show the relevance of large local deviations of mobility values of carrier electrons, particularly for traps near the source end of the channel. As a case study, jitter in an oscillator is simulated. It is shown that the methodology properly addresses open issues in the literature, by properly accounting for bias-dependent, non-stationary statistic of RTN phenomena relevant to the design of integrated circuits.

1/f Noise: threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps

Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intra-die and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation--two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO2 interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO2 interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.