Random Access Memory Cell Research Articles

Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing

This brief deals with the impact of spin-transfer torque magnetic random access memory (STT-MRAM) cell based on double-barrier magnetic tunnel junction (DMTJ) on the performance of a two-layer multilayer perceptron (MLP) neural network. The DMTJ-based cell is benchmarked against the conventional single-barrier MTJ (SMTJ) counterpart by means of a comprehensive evaluation carried out through a state-of-the-art device-to-algorithm simulation framework. The benchmark is based on the MNIST handwritten dataset, Verilog-A MTJ compact models developed by our group, and 0.8 V FinFET technology. Our results point out that the use of DMTJ-based STT-MRAM cells to implement digital embedded non-volatile memory (eNVM) synaptic core allows write/read energy and latency improvements of about 53%/61% and 66%/17%, respectively, as compared to the SMTJ-based equivalent design. This is achieved by ensuring a reduced area footprint and a learning accuracy of about 91%. Such results make the DMTJ-based STT-MRAM cell a good eNVM option for neuro-inspired computing.

Ultra-low leakage static random access memory design

An ultra-low leakage static random-access memory (SRAM) cell structure with 8 transistors is proposed in this paper. Compared to the 6T SRAM and other existing 8T SRAM cells, leakage power of the proposed cell in hold mode reduced significantly. The stability parameters of the proposed cell are calculated using butterfly method and also N-curve method. Proposed SRAM achieves better write margin with slightly less read margin than 6T SRAM. Proposed technique consumes 790 PW of power in hold mode, which is very less compared to other existing techniques. Therefore, the proposed cell is appropriate for hold mode applications. The simulations are carried out by using Cadence (Virtuoso Schematic and layout editor) tools with GPDK45-nm technology.

Multiscale Modeling of Metal-Oxide-Metal Conductive Bridging Random-Access Memory Cells: From Ab Initio to Finite-Element Calculations

Continuum modeling is a popular, computationally efficient technique that can shed light on the resistance-switching properties of conductive bridging random-access memory (CBRAM) cells. Traditional models typically rely on many fitting parameters, but this approach uses material parameters extracted either from either ab initio or machine-learned empirical calculations. As proof of concept, the authors apply the computational framework to an SiO${}_{2}$-based CBRAM cell, and reveal the relevance of Joule heating in nanoscale devices. With the proposed multiscale methodology it is possible to explore the potential of not-yet-fabricated memory cells, and to optimize their design reliably.

Schmitt Trigger 12T1M Non-volatile SRAM cell with improved process variation tolerance

This paper presents a Schmitt Trigger (ST) based 12T1M non-volatile static random-access memory (nvSRAM) cell which significantly provides tolerance against process variations. The memristor M1 is connected between internal node Q and bitline RBL through read pass transistor. The impact of process variation is studied on margin and delay performances of proposed and existing read decoupled (RD) nvSRAM cells. The proposed cell achieves 1.62X, 1.17X and 1.33X higher write, read and hold margins, respectively, in comparison to existing RD nvSRAM cells. Furthermore, the maximum reduction in write, read and hold failure probabilities by 105×, 104× and 104×, respectively, is observed for proposed cell. The overall Vmin of proposed cell is found as 425 mV which is minimum among the existing RD counterparts. In addition, there is significant reduction in leakage power consumption and write/read delay deviation for the proposed cell. The store/restore performance of the proposed cell is same as most of the considered cells. All the comparison are made using 32 nm CMOS PTM model and at Vdd = 0.6 V. The effect of supply voltage variation is also studied on the performance of proposed and existing RD nvSRAM cells for the sake of completeness.

A carbon nano-tube field effect transistor based stable, low-power 8T static random access memory cell with improved write access time

Carbon nanotube field effect transistor (CNTFET) is swiftly becoming an alternative to conventional CMOS transistors due to superior transport properties, improved current handling characteristics, and better gate control. This work presents a new Carbon nanotube field effect transistor (CNTFET) based low power, stable static random access memory (SRAM) cell design with reduced write delay. The proposed eight-transistor (8T) CNTFET-based SRAM cell improves read/write static noise margin by 1.98×/1.25×, respectively, at 0.3 V compared to conventional 6T SRAM that uses similar CNTFET parameters. The write access time and leakage power of the proposed cell are improved by 1.90× and 2.14×, respectively, compared to the conventional 6T design. The proposed design parameters are also compared with two already presented 8T SRAM cells. The simulation is performed with the Cadence Virtuoso using the Stanford University 32 nm CNTFET Verilog model.

Bit-line leakage current tracking and self-compensation circuit for SRAM reliability design

For low voltage CMOS static random access memory (SRAM) cells, the leakage current on bit-lines will slow down the reading operation and even lead to error reading. Herein we report a 4B4C circuit composed of 8T SRAM arrays, four bit-lines and four coupling capacitors to track and compensate the bit-line leakage current (BLLC). The assistant bit-lines are used to control the connection of capacitors. The coupling capacitors are used to compensate voltage losses caused by the BLLC, and improve the maximum tolerable current from primary bit-line. The timing diagram and output waveforms verify the compensatory effects of coupling capacitors. The 4B4C circuit shows fast reading operation and increases the maximum tolerable leakage current to 17.8 times compared with conventional circuit at FS process corner. The 4B4C circuit can keep 100% correct reading till 200 μA from Monte Carlo simulations. The 4B4C circuit enhances SRAM reading reliability and shows huge potential in very-large scale memory arrays.

Fowler–Nordheim Stress-Induced Degradation of Buried-Channel-Array Transistors in DRAM Cell for Cryogenic Memory Applications

The degradation of the fin-type buried-channel-array transistor (BCAT) in dynamic random access memory (DRAM) cell is investigated under Fowler–Nordheim stress at various temperatures, including 77 K. While the increase in the OFF current is dominated by the Shockley–Read–Hall junction leakage, the threshold voltage shift ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V}_{T}$ </tex-math></inline-formula> ) comprises a positive component due to the interface trap generation and a negative component resulting from the electric field concentration-induced charge trapping into the gate insulator bulk, with respective activation energies of 0.22 and 0.13 eV. Furthermore, based on the consistency between the experimentally decomposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Delta } {V}_{T}$ </tex-math></inline-formula> components and the simulated ones, it is found that the anode hole injection dominates the degradations of the wordline-active operation and refresh time in cryogenic DRAM.

Synaptic plasticity and non-volatile memory characteristics in TiN-nanocrystal-embedded 3D vertical memristor-based synapses for neuromorphic systems.

Although vertical configurations for high-density storage require challenging process steps, such as etching high aspect ratios and atomic layer deposition (ALD), they are more affordable with a relatively simple lithography process and have been employed in many studies. Herein, the potential of memristors with CMOS-compatible 3D vertical stacked structures of Pt/Ti/HfOx/TiN-NCs/HfOx/TiN is examined for use in neuromorphic systems. The electrical characteristics (including I-V properties, retention, and endurance) were investigated for both planar single cells and vertical resistive random-access memory (VRRAM) cells at each layer, demonstrating their outstanding non-volatile memory capabilities. In addition, various synaptic functions (including potentiation and depression) under different pulse schemes, excitatory postsynaptic current (EPSC), and spike-timing-dependent plasticity (STDP) were investigated. In pattern recognition simulations, an improved recognition rate was achieved by the linearly changing conductance, which was enhanced by the incremental pulse scheme. The achieved results demonstrated the feasibility of employing VRRAM with TiN nanocrystals in neuromorphic systems that resemble the human brain.

DESIGN OF A 6T SRAM CELL WITH MINIMAL POWER USING CADENCE VIRTUOSO

It has proven challenging for VLSI designers to lower leakage power at the nanoscale level. This is because high- end gadgets, battery-operated portable pads, and other communication tools are in high demand. Memories are made up of static RAM and dynamic RAM. SRAM has had a significant impact on the worldwide VLSI market sinceit is preferred over DRAM because to its rapid read and write access times. Using a 6T static random access memory cell, this study's novel approach to lowering leakage current at various technologies has been put forth. To reduce the 6T SRAM cell leaking power, three source biasing techniques are used. At 45 nanometer and 90 nm technology nodes, the three techniques are NMOS diode clamping, PMOS diode clamping, and NMOS-PMOS diode clamping. The implementation of a 6T SRAM cell using the Multiple Threshold CMOS (MTCMOS) technique at 45nm technology is also emphasised in this article. Using the cadence virtuoso tool, the simulation is completed and different power dissipations are examined for 45 nm and 90 nm technologies, respectively, at supply voltages of 0.45 V and 0.9 V. Comparing PMOS clamping to the other two suggested techniques, an average power reduction of 82.19% was observed.

Optimization Techniques for Reliable Low Leakage GNRFET-Based 9T SRAM

We present a low-leakage graphene nano-ribbon transistors (GNRFETs)-based static random access memory (SRAM) cell in 16nm technology that operates near the sub-threshold region in this study. In comparison to conventional Si-CMOS technology, the proposed cell improves read stability and writeability by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.67\mathbf {\times }$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.14\mathbf {\times }$ </tex-math></inline-formula> , respectively. The proposed cell considerably outperforms the existing 9T SRAMs cell in terms of power consumption, latency, read stability, and write-ability, according to the HSPICE simulation. In addition, at the low supply voltage of 325mV, the multi-threshold approach and transistor optimizations are used to improve the read static noise margin (RSNM). The proposed cell’s overall power consumption is lowered by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4161\mathbf {\times }$ </tex-math></inline-formula> when compared to a conventional 6T SRAM cell while using the multi-threshold approach in the write port. Device optimization and the multi-threshold approach, which enhances read and write performance, can considerably minimize read and write delays.

Formation of Remote Quantum Point Contact Inside Dielectric Medium of an AlO x /SiO x ReRAM

Remote quantum point contact (QPC) far from the metal electrodes was observed in forming free aluminum oxide (AlOx)/silicon oxide (SiOx) resistive random access memory (ReRAM) cell, which was resolved at low bias. QPC behavior of the cell was attributed to confined oxygen vacancies across uncorrelated narrow grain boundaries of intermediate O3 treated thin AlOx layer of the stack, which was designed to restrict vacancy channeling between the two immediate reservoirs; i.e., from beneath SiOx to the top as-deposited AlOx layer. From time dependent dielectric breakdown (TDDB) characteristics of the cell while assessed under low stress biases, we found one to one correspondence between TDDB and its bias dependent QPC. Furthermore, we found that, under steady state and especially at low biases progressive breakdown (PBD) of the dielectric exhibited two-level random telegraph noise (RTN) like conductance fluctuations, which occurred in the magnitude of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${G}_{{0}}$ </tex-math></inline-formula> or in its multiples depending on applied bias to the cell, that demonstrated a correlation between electron trapping and maximum QPC instability during filament growth. Low voltage QPC-based switching under dc bias sweep, its correlation with TDDB and RTN under the steady state thus provided us a framework to analyze the evolution of QPC well before reaching the SET state in an AlOx/SiOx cell, which is different from the usual QPC evolution as found near contact regions in a conventional SiOx cell without accompanying engineered AlOx barrier.

Performance Analysis of 6T SRAM and ONOFIC Cells

Background: As the technology node scales down to a deep sub-micron regime, the design of static random-access memory (SRAM) cell becomes a critical issue because of increased leakage current components. These leakage current components prevent the designing of a low-power processor as a large portion of the processor power is consumed by the memory part. Objective: In this paper, an SRAM cell is designed based on the ON/OFF logic (ONOFIC) approach. Static noise margin (SNM) of the cell for the different states are calculated and evaluated by using the butterfly as well as noise (N) curves with the help of Cadence tools at 45 nm technology node. Methods: ONOFIC approach reduces the leakage current components, which makes a low power memory cell. A performance comparison is made between the conventional six-transistor (6T) SRAM cell and memory cell using the ONOFIC approach. Results: Low value of power delay product (PDP) is the outcome of the ONOFIC approach as compared to conventional cells. ONOFIC approach decreases PDP by 99.99% in case of hold state. Conclusions: ONOFIC approach improves the different performance metrics for the different states of the SRAM cell.

Novel radiation-hardened SRAM for immune soft-error in space-radiation environments

As the feature size of transistors scaling down, the integration density of memory circuits such as Static random access memory (SRAM) cells increases, and they are more sensitive to Single event effect (SEE). The Single event multiple node upset (SEMNUs) caused by charge sharing effect is becoming a major concern in memory circuit design. In this paper, a new radiation-hardened SRAM cell (NRHC-14T) is proposed on the basis of considering the radiation-hardened and the operating performance of the basic circuit. The circuit uses polarity hardening technology to reduce the number of sensitive nodes, and can recover from Dual-node upset (DNU) on the basis of all single-node upset (SNU) recovery. Compared to other radiation-hardened cells, NRHC-14T cell than We-Quatro, DICE, SAR14T, RSP14T, RHPD-12T, QUCCE12T, and SEA14T increased by 60.12 %, 9.22 %, 21.39 %, 84.34 %, 17.92 %, 100.58 %, and 129.48 % of the writing speed, and saved by 34.28 %, 57.14 %, 22.85 %, 11.43 %, 68.57 %, 34.28 %, and 79.99 % of the power consumption, respectively. In addition, NRHC-14T has better stability, the highest Critical charge (Qcrit) and the best overall performance. The cell proposed in this paper can be well used to aerospace electronic devices and work stably in space radiation environment by virtue of its excellent radiation-hardened ability and good overall performance.

Design of Static Random-Access Memory Cell for Fault Tolerant Digital System

This paper comparatively analyzes the static random-access memory (SRAM) cell designs for fault tolerance. Since SRAM cells are sensitive to radiation-induced single event upsets, various circuit-level approaches have been applied. Compared to the conventional SRAM cell circuits, one possibility is adding redundant storage nodes by means of additional transistors. The strength and weakness of the SRAM cells in terms of various performance aspects—speed, area, power, stability, fault tolerance, etc.—according to the design approaches are compared analytically and discussed. The discussion concludes that, in the future, it is paramount to develop an SRAM cell design with a mitigated trade-off between read/write performance and SEU tolerance.

Design of a stable single sided 11T static random access memory cell with improved critical charge

AbstractRadiation‐induced soft errors are becoming a key challenge in satellite‐based communication. The worst‐hit component of such devices is static random‐access memory bit‐cells, owing to their high density, large area, and low‐operating voltage. The unsuitability of conventional 6T SRAM for this purpose is ascertained by weak stability constraints, higher variability during process variations, and less tolerance capability in such a harsh environment. In this work, we have presented an improved, feedback charge‐boosted, and read decoupled 11 transistors based (FC11T) SRAM cell. Its performance is assessed by comparing it with other low power, high stability, and soft‐error‐immune SRAM cells, namely, Asymmetric 8T (AS8T), Quatro 10T, PPN based 10T (PP10T), and loop cutting 10T (LC10T) cells over various design metrics. The attained observations establish that the proposed FC11T shows 1.13×/1.38×/0.90×/1.04×/1.03× improvement in critical charge compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The read access time of proposed FC11T cell is reduced by 1.31×/1.17×/1.31×/1.41×/1.01× compared to 6T/PP10T/AS8T/Quatro10T/LC10T cell. The proposed cell further strengthens read stability by 1.97×/0.98×/1.91×/1.24×/1× when equated to 6T/PP10T/AS8T/Quatro10T/LC10T cell. Improved Inter‐cell and Intra‐cell soft error ratios represent improved soft error mitigation capability of the proposed 11T cell over 0.5 to 1 V supply voltage and 27 to 125 C temperature variation range. In addition to this, the proposed 11T cell also shows improved read stability and writability.

Cross-Coupled Gated Tunneling Diodes With Unprecedented PVCRs Enabling Compact SRAM Design—Part II: SRAM Circuit

In Part I of this article, we present a novel device, i.e., a cross-coupled gated tunneling diode (XTD), which exhibits negative differential resistance (NDR) with peak-to-valley current ratios (PVCRs) exceeding 105. In this part of this article, based on the XTD, we introduce a compact static random access memory (SRAM) cell using a one-transistor and two-XTD (1T-2X) design. The layout of the SRAM cell as well as a detailed analysis of the cell behavior and SRAM array performance are presented. In particular, our simulation results show that the 1T-2X SRAM cell can achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$70\times $ </tex-math></inline-formula> improvement in standby power with ~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> area reduction compared to standard CMOS SRAM.

Reliable and low power Negative Capacitance Junctionless FinFET based 6T SRAM cell

The increasing demand of portable gadgets for emerging VLSI applications call for the low power 6 T static random-access memory (SRAM) cell design. In this work, a 6 T SRAM cell has been designed using Negative Capacitance Junctionless FinFET (NC-JL FinFET) device. Further, the NC-JL FinFET based 6 T SRAM cell is evaluated for its power, stability and delay performance for read, write, and hold states and compared with conventional JL FinFET and published JL FinFET based SRAM. To investigate the reliability, the impact of ferroelectric thickness (TFE) and supply voltage (VDD) on the performance of NC-JL FinFET SRAM has also been investigated. It is shown that NC-JL FinFET SRAM dissipates 20% and ∼33% less static and dynamic power, with 1.2-, 1.5- and 1.18-times enhanced static noise margins in read, write, and hold state, respectively than JL FinFET SRAM. It also provides 37% and 20% faster read and write operations.

Insights into few-atom conductive bridging random access memory cells with a combined force-field/ab initio scheme

We present a simulation framework to simulate the switching behavior of Ag/a-SiO2 conductive bridging random access memories (CBRAM). Whereas the dynamics of the switching process is investigated with classical molecular dynamics simulations using a force-field, the electrical properties are determined through ab initio calculations. With a structural analysis of the oxide, we shed light on the switching mechanism, which relies on preferred channels containing wide SiO2 rings through which Ag+ ions migrate. Also, we demonstrate that moving only few atoms in such channels can change the resistance state by several orders of magnitude.

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 μA/μm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future.

Fully printed ZnO-based valency-change memories for flexible and transparent applications

Printable and flexible memory devices have attracted a great deal of attention in several emerging technological applications for the development of flexible electronics, such as interconnections/wearables/smart devices for the internet of things (IoT). In this work, we report on the fabrication of flexible, transparent, and fully inkjet-printed resistive random access memory (ReRAM) cells using poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS)/ZnO/PEDOT:PSS structures. The electrical characteristics were studied, including the determination of space charge limited conduction (SCLC) as the dominant charge transport mechanism. In addition, the bending performance and the transparency of the devices was tested in order to confirm the reliable operation and reproducibility of the cells. The switching for the printed structures of PEDOT:PSS/ZnO/PEDOT:PSS was led through the formation and dissolution of a stable oxygen vacancy filament, as confirmed by conductive atomic force microscopy. While the conduction mechanism for the high resistance state (HRS) was attributed to the SCLC mechanism. The switching of the memory cells, their endurance and retention properties were analysed and indicated the stability of the HRS and low resistance state for more than 104 cycles and 105 s comparable to ZnO-based ReRAM produced by clean-room techniques. The study of the mechanical flexibility of the cells shows that up to 700 bending cycles can be reached without significantly changing the switching characteristics.