Ramp Signal Research Articles

A Novel Adjustable Parameters PID Control of Dual-motor Driving Servo System

ABSTRACTIn order to reduce the adverse effect of backlash nonlinearity on dual-motor driving servo system, the system model is firstly described. Then a novel adjustable parameters PID control algorithm combining fuzzy RBF neural network control with PID control is proposed for the first time, and analyzed its stability. In the simulation analysis, the system track step signal, ramp signal and sine signal respectively. Simultaneously, different interference signal were applied to system output when system tracking different signal. Simulation results show that the proposed control algorithm has smaller tracking error and better anti-interference ability than that of mere PID control, because PID parameters can automatically be adjusted as the system tracking error changes. In the end, white noise interference signal are applied to system output in the experiment analysis. The experiment results also validate the higher tracking accuracy and stronger robustness of the proposed control algorithm than that of PID control.

A 6.3 GHz high bandwidth voltage-to-time converter with high linearity

A voltage-to-time converter (VTC) architecture with high-bandwidth SFDR performance is presented. This VTC circuit is compatible with high-speed, high-bandwidth RF ADC systems. The proposed VTC utilizes the bottom plate sampling of the capacitor. A constant current source charges the capacitor and generates a ramp signal, which passes through the threshold comparator to output the time pulse signal. An independent sampling process RC loop is adopted to improve the input bandwidth of VTC. The circuit architecture of the cascode current source charging directly to the capacitor provides the linearity of the VTC. A novel bootstrapped switch is employed to further improve the linearity of VTC. The prototype VTC was fabricated in a 65 nm CMOS process with an active area of 0.008 mm2. It exhibits an SNR of 62.7 dB and an SFDR of 54.6 dB for an input frequency of 6 GHz and a sampling rate of 500 MS/s under the TT process corner simulation.

Adaptive velocity-dependent proportional-integral controller for high-speed atomic force microscopy.

High-speed atomic force microscopy (AFM) has been rapidly developed in recent years. To reduce the oscillation of the scanner, a single-tone sinusoidal wave is widely used as a scanning wave rather than a triangular wave in high-speed AFM. However, the sinusoidal wave is nonlinear, resulting in a nonconstant relative linear velocity between the sample and the tip while scanning in the x-direction. If a traditional proportional-integral controller is still used as a feedback controller in the z-direction, the control errors will be enormous. Therefore, the paper proposes a new adaptive velocity-dependent proportional-integral controller. The relationship between the proportional-integral parameters and the linear velocity is achieved by fitting the experimental results. The adaptive and traditional controllers are compared against each other in some examples. The experiments demonstrate that the adaptive controller decreases the control errors in the z-direction to a half, which provides more precise AFM images. LAY DESCRIPTION: Typically, the scanner follows a triangular waveform in fast axis (x-axis), and follows a very slow ramp signal in the slow axis (y-axis) of conventional AFM. This scanning mode can be called raster scan. However, the triangular waveform contains high-order Fourier harmonics, vibrating the scanner and distorting the image easily. In high-speed AFM, the effect of the high-order Fourier harmonics will be more severe. The above problems can be solved by replacing triangular waves with single-tone sinusoidal waveform. Therefore, the sinusoidal-raster scan and nonraster scan based on the sinusoidal waveform are widely used in high-speed atomic force microscopy. However, the nonlinearly scan path will cause a variable relative linear velocity between the sample and the tip. If a standard proportional-integral controller is still used as a feedback controller in Z direction, the control errors will be large, and this difference will be evident at high-speed scanning. Thus, the paper proposes a new adaptive velocity-dependent proportional-integral controller to solve this problem. Experiments show that the control errors obtained by using the adaptive controller is about a half of that without using it. These illustrate that the proposed method can improve the image quality of the AFM at both low and high scan speeds.

ANN-based Maximum Power Point Tracking for a Large Photovoltaic Farm Through Wireless Sensor Networks

Background: A novel system for the usage of Maximum Power Point Tracking of an expansive Solar Photo Voltaic (SPV) farm subjected to conceivable incomplete shading is displayed in this paper. The SPV farm being spread over an expansive territory a remote sensor organize is utilized for checking the sun based protection in the region of each board. The motivation behind the remote sensor organize is to screen the sunlight based protection at various areas near each of the PV board from the tremendous region of the photograph voltaic homestead comprising of countless voltaic boards. The observed protection information is utilized by a prepared. Artificial Neural Network to locate the ideal DC terminal voltage to be kept up over the general DC terminals of the photograph voltaic ranch. All the PV boards are associated in arrangement association with the fundamental bye pass diodes. The DC control accessible at the yield terminals of the SPV cultivate is first DC to DC changed over with a Positive Output Luo Converter (POLC) and bolstered to a heap. A MATLAB Simulink based reproduction was created to approve the proposed system. Methods: Maximum Power Point Tracking based on Artificial Neural Network through wireless sensor networks. Results: As the result of the proposed idea and its implementation in MATLAB we have two sets of results. In either case the input is a vector of 40 elements and the output of the first segment of the work is the estimation of the threshold PV terminal voltage that will guarantees maximum power point operation. In the first case we have the MATLAB SIMULINK implementation of the basic configuration of the forty PV panels arranged in series connection and we have provided a facility to edit the solar insulation levels pertaining to the individual PV panels. In this first configuration we have set a continuously variable PV current for all the panels and the PV current for all the panel are the same. Using this setup, for any combination of solar insulation pattern of the forty panels the overall PV curve and the overall VI curve can be drawn in MATLAB. As the simulation runs the PV current is changed from 0 to the maximum or the short circuit current level in a slowly rising manner implemented using a ramp signal. </P><P> During this period the total power output and the terminal voltage of the PV farm are sent to the work space and the data is thus collected in the workspace of MATLAB. Using basic MATLAB commands the maximum power output and the PV terminal voltage corresponding to the maximum power output are obtained. The PV current at maximum power output condition, the corresponding PV farm terminal voltage, the maximum power output recorded at this condition all correspond to the present insulation vector condition. This way, by changing the elements of the insulation for all the forty panels in a random manner we obtain for each case the Ipmax[i], Pmax[i], Vpmax[i] and this corresponds to insulation[n,i]. Where n is the number of panels, in this case 40 and i the ith experiment. In each experiment the solar insulation level of all the forty panels can be changed and the parameters Vpmax[i], Ipmax[i] and Pmax[i] can be obtained. The value of the harvested power as found from the characteristics for any given set of insulation is denoted as the estimated power. The value of power as obtained from the proposed ANN SMC POLC combination is denoted as the Actual Power. Conclusion: A wireless network based insulation monitoring has been done. An ANN based MPPT algorithm has been developed that gives the reference MPP voltage. The sliding mode control scheme uses the reference voltage and produces the switching pulses for the POLC. The ANN had been trained with a number of combinations of different insulation values falling on each of the forty panels and the ANN gives the correct reference voltage for any combination of insulation levels that were not used while training. The sliding mode controller uses this reference voltage and gives the switching pulses to the POLC that harvests the maximum power output to the RL load. The proposed system has been implemented in the MATLAB SIMULINK environment and has thus been validated. The obtained results have been compared against the maximum power output values that could be derived from the characteristic curves obtained for the given combination of insulation levels. The proposed system gives results very close to the values obtained from the characteristics. As a future work the proposed idea can be validated using hardware based experimental setup.

Discussion of “Queue Storage Design for Metered On-Ramps” by Zhongren Wang

Abstract This article presented a discussion on a research paper entitled “Queue Storage Design for Metered On-Ramps”, published by the International Journal of Transportation Science and Technology on March 2013 (Volume 2, Issue 1, Pages 47–63). This discussion first summarized the contributions of the paper under discussion, and emphasized a critical insight presented by the paper under discussion that designing queue storage length as a percentage of peak hour on-ramp demand. Then, this article discussed the potential factors that may affect queue length estimation results, including different traffic flow arrival patterns between arterial-to-freeway ramps and freeway-to-freeway connectors, queue length as a function of demand-to-capacity ratio instead of on-ramp traffic volume, and errors caused by the stochastic nature of traffic flow when using field measured queues. Lastly, this article outlined methods to solve these limitations, and presented preliminary insights into the development of metered on-ramp queue storage length design guidelines considering the impacts of ramp geometric features and signal timing schemes of the upstream intersection.

A Joint Least Squares and Least Absolute Deviation Model

We propose a joint least squares and least absolute deviations (JOLESALAD) model, show that the proposed model can cover least absolute shrinkage and selection operator (LASSO) and two of its variants, namely the generalized LASSO (gLASSO) and the constrained LASSO (cLASSO), and prove that under a full rank condition, the JOLESALAD can be transformed into cLASSO. Based on this equivalency, rich tools currently available for LASSO models can be applied to solve gLASSO and cLASSO. As an example of illustration, we demonstrate an application of the proposed model to the restoration of a noisy ramp signal that needs proper use of penalty term.

Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation

This paper presents the design of linear ramp generator and digital BIST for an on-chip ADC testing. It replaces the costly and time-consuming traditional mixed signal test methods like DSP-based testing, ATE, etc. The proposed on-chip analog ramp generator uses only a few transistors to generate linear ramp signal. A TIQ comparator based 8-bit flash ADC is taken under test. The output response of the ADC is analyzed in the digital BIST to measure the primary nonidealities affecting the linearity and accuracy of the data conversion. In testing, ADC generates the digital data sequence as a test pattern in response to the ramp input while digital BIST estimates the conversion error. This method does not require DAC and any additional components which increase the area overhead of ADC test. The complete design of ramp generator is integrated with TIQ flash ADC and verified in 0.18[Formula: see text][Formula: see text]m CMOS technology with 1.8[Formula: see text]V of the power supply and 100[Formula: see text]kHz of the input frequency. Measurement of nonidealities shows that the design of an 8-bit flash ADC has good accuracy in data conversion with the differential nonlinearity of [Formula: see text]0.24/[Formula: see text]0.17[Formula: see text]LSB and integral nonlinearity of [Formula: see text]0.44/[Formula: see text]0.04[Formula: see text]LSB.

Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs

This paper presents an on-chip stepwise ramp stimulus generator aimed at static linearity test applications for analog-to-digital converters (ADCs). The proposed ramp stimulus generator is based on a simple switched-capacitor integrator with a constant dc input. The integrator has been conveniently modified to produce a very small integration gain proportional to the capacitance difference of two capacitors, in such a way that the resulting stepwise ramp signal at the output has a step size below the least significant bit (LSB) of the target ADC under test. In order to verify the feasibility of the proposed ramp generation technique, this paper details the design and experimental characterization of a proof-of-concept stepwise ramp generator in a 65-nm CMOS technology. Experimental results on 15 fabricated samples show an average linearity of 14.5 effective bits in a differential output range of ±2 V. Moreover, a discrete-time static linearity measurement strategy is proposed and, as a proof-of-concept validation, it is verified on an off-the-shelf 11-bit ADC using the fabricated generator samples. Experimental results show an accuracy of ±0.3 LSB in the measurement of the integral nonlinearity of the ADC under test.

Error Detection of Data Conversion in Flash ADC using Code Width Based Technique

Abstract The high integration density of the complex electronic system requires the multi-functional testing facility to ensure the accuracy of the circuit function. In addition, the wide population of submicron technologies results in the persistent requirements of high precision analog and mixed-signal (AMS) circuits. In the complex, high-density circuits, observing the correctness of output are limited due to the limitations of input and output pins which develop the AMS circuit test as very difficult and expensive. A digital built-in self-test (BIST) scheme has been presented in this paper for testing an analog to digital converter (ADC) in the time domain. The testing scheme consists of the linear analog ramp generator, ADC as a circuit under test, output response analyzer and a BIST controller. Bootstrap linear ramp generator is used to generate the linear analog ramp signal which is applied to ADC to develop the digital word sequence for testing. Among various types of ADCs, here a Flash ADC has used since it is fastest and accurate in digital conversion. A Flash ADC has been designed with the seven-bit resolution and tested using the proposed digital BIST scheme. The ADC comprises a sample-hold circuit, 2N -1 comparator, XOR gates, and encoder block. The output response analyzer verifies the digital output sequence to validate the static test parameters of ADC called monotonicity, missing codes, DNL, and INL error. The BIST controller generates the control signals to control the test sequence. The complete test sequence of ADC BIST has simulated in Tanner EDA with TSMC 0.18um technology. ORA is used to analyze the presence of monotonicity, missing codes, DNL and INL error in the ADC output.

Positive and Negative Feedback for Linearity Improvement and PVT Compensation of the Ramp Generator

Linearity of ramp signals is one of the most important aspects for many applications such as single-slope analog to digital converters (ADCs); another important aspect is the total power dissipation. Applications like high-resolution single-slope ADCs that can be used in portable devices demanded accurate ramp generator with low power dissipation. This paper presents a low power ramp generator with linearity improvement that achieved by a positive feedback circuit and negative feedback for compensation of the variations in process, voltage and temperature. Derived equations of the proposed ramp generator circuit show that linearity of the output ramp, with proper choosing of device sizes, can be enhanced significantly. Also, for proving of linearity enhancement, the circuit design and post-layout simulations were done in TSMC 0.18[Formula: see text][Formula: see text]m and 90[Formula: see text]nm CMOS technologies. Simulation results show that linearity of the circuit improved by a factor of 8 and total ramp resolution improved about 3 bit, whereas power dissipation of the circuit is about 8[Formula: see text][Formula: see text]W and entire layout core area is near 800[Formula: see text][Formula: see text]m2.

A FHD 1080, 120 fps CMOS image sensor with two step SS-ADC

This paper presents a full high definition 1920 × 1080 pixel, 120 frames/s CMOS image sensor with two-step single-slope (TS-SS) ADC. The column-parallel TS-SS ADC and binary subtractor are used to convert photodiode voltage to the final 10-bit digital data. Therefore, there is no need for the pixel readout, noise suppression or comparator offset cancellation circuits to be used in the columns. A new ramp signal generator is proposed to generate 32 concurrent and identical ramp signals. TS-SS ADC improves the conversion speed while reducing the power consumption level as well. The proposed image sensor has been designed using TSMC 0.18 μm 1-poly 4-metal standard process. The simulation results show that the total comparator referred noise to the FD node in 1 Hz–100 MHz range is 0.574 mV and, also the total power consumption is about 100 mW.

Active EMI Reduction Using Chaotic Modulation in a Buck Converter with Relaxed Output LC Filter

DC-DC buck converters are widely used in portable applications because of their high power efficiency. However, their inherent fast switching releases electromagnetic emissions, making them prominent sources of electromagnetic interference (EMI). This paper proposes a voltage-controlled buck converter that reduces EMI by using a chaotic pulse-width modulation (PWM) technique based on a chaotic triangular ramp generator. The chaotic triangular ramp generator is constructed from a simple on-chip chaotic circuit linked with a symmetrically triangular ramp circuit. The proposed converter can thus operate in the chaotic mode reducing the EMI without requiring any EMI filters. Additionally, using the triangular ramp signal can relax the requirement for a large LC output filter in chaotic mode. The effectiveness of the proposed scheme was experimentally verified with a chaotic triangular ramp generator embedded in a voltage-mode controller buck converter using a 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) process. The measurement results from a prototype showed that the EMI improvement from the proposed scheme is approximately 14.53 dB at the fundamental switching frequency with respect to the standard fixed-frequency PWM reference case.

Design of an FPGA based DPLL with fuzzy logic controllable loop filters with application customization capability

The carrier recovery loops are important in carrier tracking approaches particularly in the presence of high dynamic stress on user receivers and noisy environment applications. The precise carrier tracking techniques are proposed in systems that are sensitive to carrier mismatches, such as terrestrial or satellite tracking systems. The fading phenomenon, phase and frequency step changes and high user dynamics are currently most important challenges in the development of robust carrier tracking systems. In this work, a novel Digital Phase Locked Loop (DPLL) is proposed using type-2 fuzzy logic controller to improve noise immunity and handling user dynamic in digital receivers with application customization capability. Due to fast and accurate decision-making by proposed fuzzy logic controller, optimal loop filter coefficients are generated for DPLL. The proposed DPLL is simulated with Xilinx System Generator Software and can be implemented on FPGA. In comparison to traditional approaches, proposed new DPLL shows better performance in response to phase step, frequency step and frequency ramp signals with acceptable settling time alongside minimum complexity in implementation and customization.

Robust leader-following output regulation of uncertain multi-agent systems with time-varying delay

In this paper, the robust analysis and design of leader-following output regulation for multi-agent systems described by general linear models is given in presence of time-varying delay and model uncertainty. To this aim, a new regulation protocol for the closed-loop multi-agent system under a directed graph is proposed. An important specification of the proposed protocol is to guarantee the leader-following output regulation for uncertain multi-agent systems with both stable and unstable agents. Since many signals can be approximated by a combination of the stationary and ramp signals, the presented results work for adequate variety of the leaders. The analysis and design conditions are presented in terms of certain matrix inequalities. The method proposed can be used for both stationary and ramp leaders. Simulation results are presented to show the effectiveness of the proposed method.

A Low-Power 12-Bit Extended Counting ADC Without Calibration for CMOS Image Sensors

This brief proposes a low-power 12-bit column-parallel extended counting analog-to-digital converter (EC ADC) without calibration for CMOS image sensors. The proposed 12-bit EC ADC uses the ${\Delta \Sigma }$ ADC and single-slope ADC (SS ADC) to convert the input voltage to the upper 4 bit and lower 8 bit, respectively. It reduces power consumption by sharing a comparator between the ${\Delta \Sigma }$ ADC and the SS ADC, and is robust to the inaccurate ramp signal. The 16-LSB linearity error of the ramp signal causes only 1 LSB linearity error of the proposed EC ADC. In addition, the proposed EC ADC improves the ADC linearity without calibration by adjusting the slope of the ramp signal in the lower 8-bit conversion phase according to the capacitance mismatch between the sampling and feedback capacitors. A test chip with 200 readout channels, each including the proposed EC ADC, was fabricated using an 0.18- ${\mu }\text{m}$ CMOS process. The measurement results show that the proposed EC ADC achieves a differential nonlinearity of +0.4/−0.3 LSB and an integral nonlinearity of +3.5/0 LSB without calibration. In addition, the measured signal-to-noise distortion ratio and effective number of bits are 65.4 dB and 10.5-bit, respectively. The measured power consumption per ADC is $22~{\mu }\text{W}$ and the best figure of merit in power efficiency is achieved to be 82 fJ/step.

Output regulation boundary control of first-order coupled linear MIMO hyperbolic PIDE systems

ABSTRACTThe work addresses the output regulation problem for coupled linear multiple input multiple output (MIMO) hyperbolic partial integro-differential equation systems with disturbances affecting the systems through the space and boundary input. The exosystems are extended to generate ramp signals and general family of polynomial signals. The system decomposition is applied through the state transformation and yields a decoupled equivalent system. Based on the decoupled form, the backstepping transformation is applied and then in the new coordinate, the full state and output-feedback regulators are designed, respectively. For the state feedback regulator, the corresponding regulator equation is obtained and its solvability conditions are provided to facilitate the regulator design and feasibility. The design of observer-based regulator is based on the decoupling of the observer error system into a PDE subsystem and an ODE subsystem so that the backstepping approach achieves stabilisation by eigenvalue assignment leading to design of observer stabilizing gains.

Digital Fuzzy Current Mode Controlled Integrated PFC Converter with External Ramp Compensation

This paper propounded a novel method of design and realization of a digital fuzzy controlled buck integrated power factor correction (PFC) converter. It derives its advantages through the low buck capacitor voltage and single control switch (SW1), which leads to reduced complex control and price. Sub-harmonic oscillations generated in the peak current mode technique can be nullified by using the ramp signal, thereby improving the overall performance of the converter. The fuzzy logic controller (FLC) is robust and effective than the conventional linear controllers like P, PI, PID. In this paper, the digital fuzzy current mode controlled integrated PFC converter with external ramp compensation signal for 100 W load operating in the universal range of voltage (90[Formula: see text]V–265[Formula: see text]V), 50[Formula: see text]Hz has been designed and implemented using MATLAB/Simulink, verified in hardware using the TMS320F2812 digital processor board, and the results are found to be complying with international regulatory standards (IEC 6100-3-2 and IEEE 519-1992).

A Comparative Study Between Cascaded FOPI–FOPD and IOPI–IOPD Controllers Applied to a Level Control Problem in a Coupled Tank System

This paper presents a novel liquid level control of a coupled two tank SISO system. Physical system is modeled from the open loop experimental response in two stages. A cascade control strategy is adopted. Fractional Order Proportional Integral (FOPI) and Fractional Order Proportional Derivative (FOPD) controllers are designed for the outer and inner loop, respectively, using frequency domain method. Similarly, conventional Integer Order Proportional Integral and Integer Order Proportional Derivative controllers are also designed to compare the performances. Reference signal tracking performance is tested with multiple step, ramp and sinusoidal reference signals. Ability of disturbance rejection is tested by adding more water into the tanks through a disturbance input channel. Experimental results reveal that the proposed FOPI–FOPD control scheme outperforms its integer order counterparts both in terms of reference signal tracking and disturbance rejection.

Quick and cost-efficient A/D converter static characterization using low-precision testing signal

The measurement of the analog-to-digital converter (ADC) output by exciting the signal generator with a high precision input signal allows the determination of ADC's static characteristics using a histogram-based approach. However, this method exhibits some limitations imposed by the input signal, including its high resolution and high linearity that are causes for concern when testing a high precision ADC. Recent research work has been trying to overcome such limitations. Nonetheless, it is necessary to discover a simple and low-cost method to measure the linearity of a high precision ADC through a low precision stimulus. This paper introduces a novel procedure that allows the relaxation of the requirements of the signal source for estimating ADC's linearity characteristics. The proposed method requires two sets of testing sources, being both ramp signals, one of low-precision and the other attenuated. Simulation and experimental results validate the proposed method in different ADCs.

A Time-Domain Digital-Intensive Built-In Tester for Analog Circuits

To solve test challenges in nanometer CMOS technologies, a time-domain digital-intensive built-in tester for analog circuits is proposed. The compact tester allows characterizations of AC response and DC gain for various analog circuits which have a low-pass frequency characteristic. By applying ramp signals to stimulate the circuit under test and measuring slopes and time delays of its responses, the testing can be simple and robust over process-voltage-temperature variations. Also, it is well suited for nanometer technologies because of its digital-intensive implementation. The tester was fabricated in 65 nm standard CMOS process and occupies 0.026 mm2.