Design of an FPGA based DPLL with fuzzy logic controllable loop filters with application customization capability

Abstract

The carrier recovery loops are important in carrier tracking approaches particularly in the presence of high dynamic stress on user receivers and noisy environment applications. The precise carrier tracking techniques are proposed in systems that are sensitive to carrier mismatches, such as terrestrial or satellite tracking systems. The fading phenomenon, phase and frequency step changes and high user dynamics are currently most important challenges in the development of robust carrier tracking systems. In this work, a novel Digital Phase Locked Loop (DPLL) is proposed using type-2 fuzzy logic controller to improve noise immunity and handling user dynamic in digital receivers with application customization capability. Due to fast and accurate decision-making by proposed fuzzy logic controller, optimal loop filter coefficients are generated for DPLL. The proposed DPLL is simulated with Xilinx System Generator Software and can be implemented on FPGA. In comparison to traditional approaches, proposed new DPLL shows better performance in response to phase step, frequency step and frequency ramp signals with acceptable settling time alongside minimum complexity in implementation and customization.