Radix-2 FFT Research Articles

Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units

Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a low-power FFT processor, because it has the lowest number of arithmetic operations among all the FFT algorithms. In the design of such processors, an efficient addressing scheme for FFT data as well as twiddle factors is required. The signal flow graph of SRFFT is the same as radix-2 FFT, and therefore, the conventional address generation schemes of FFT data could also be applied to SRFFT. However, SRFFT has irregular locations of twiddle factors and forbids the application of radix-2 address generation methods. This brief presents a shared-memory low-power SRFFT processor architecture. We show that SRFFT can be computed by using a modified radix-2 butterfly unit. The butterfly unit exploits the multiplier-gating technique to save dynamic power at the expense of using more hardware resources. In addition, two novel address generation algorithms for both the trivial and nontrivial twiddle factors are developed. Simulation results show that compared with the conventional radix-2 shared-memory implementations, the proposed design achieves over 20% lower power consumption when computing a 1024-point complex-valued transform.

A Hardware/Software Co-design of High Efficiency AAC Audio Decoder

This paper presents an implementation of hardware/software co-design for high efficiency advanced-audio-coding (HE-AAC) audio decoder. The decoder system is partitioned into software and hardware part throughout the computation analysis. In our design strategy, the bitstream parser and lower complexity part are performed by software solution, and the higher complexity part is computed by hardware solution. As in the dedicated hardware, four units are developed to cope with IMDCT, analysis quadrature mirror filterbank (AQMF), HF generator and envelope adjuster and synthesis quadrature mirror filterbank (SQMF). To support the various types of transformation-based functions in HE-AAC decoding, we manipulate it based on the decomposition of common radix-2 FFT method. The hardware part is designed as an intellectual property (IP) by TSMC 90 nm library. As a cost-effective design, it consumes about 150 K gates and executes at a very low operation frequency with 1.75 MHz. The power consumption is only 7.69 mW with some low power design considerations. Moreover we construct the overall system including the wrapper design and embedded platform as a system on a programmable chip (SOPC) platform. With this design approach, over 91.26 % processor-based loading can be saved and substituted by this hardware IP.

Design of area and power efficient Radix-4 DIT FFT butterfly unit using floating point fused arithmetic

In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time (DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.

Implementation of LMS-ALE Filter Using Vedic Algorithm

ALE or adaptive line Enhancers are special kinds of adaptive filters widely used in noise cancellation circuits. In circuits where we don’t have any prior knowledge of signal and noise, fixed filters unit never works good. Among adaptive filter ring algorithms LMS algorithm is very common, in our work also we use LMS algorithm. LMS-ALE filters removes the sinusoidal noise signals present in the channel by calculating the filter coefficients in every iteration. LMSALE filter has large number of multiplier units. FFT or Fast Fourier Transform blocks present in LMS algorithm again consist of large array of multiplier units. Optimization of LMS-ALE filter lies must start from optimization of multiplier blocks. Here we use Vedic “Vertical and crosswise algorithm” for multiplier design. When compared to conventional booth multiplier based LMS-ALE filter units, Vedic multipliers gives more performance in areas like resource utilization, power requirement, delay etc. The work includes designing Vedic multipliers, complex Vedic multipliers, redesigning Radix-8 FFT using Vedic multipliers, redesigning LMS block using Vedic FFT, redesigning LMS ALE filter using Vedic multipliers and Vedic LMS blocks. Major part of design is done in verilog using Xilinx ISE design suite. ADC block present in LMS-ALE filter is done in Matlab version 2013.

High-speed design for mixed radix FFT algorithm based on multi-bank memory strategy

A multibank memory structure is introduced for mixed radix FFT algorithms to improve the real-time performance. In this structure, only one butterfly unit implementing mixed radix butterfly computation is required and the FFT computation keeps continuous. At last, comparisons are made to prove that the method in this paper is valid.

An efficient design for general mixed radix FFT processors

An efficient design for general mixed radix FFT processors

Error Rate Performance of OFDM Transceiver on Software-defined Radio

2 Abstract: This work is focused on an efficient model of OFDM transceiver with the help of software-defined radio (SDR) system with reconfigurable architecture for wireless communications. SDR possesses revolutionary developments such as algorithm implementation of digital communication and increased computing capabilities. In the paper, OFDM system design and implementation with novel technology development is the primary focus to be studied. Different modulation techniques of OFDM system and other related concepts like PAPR also taken into consideration in order to design the OFDM System. FEC coding is performed by suggesting Convolutional coders. In this paper, bit error rate and symbol error rates performance are analyzed by varying bits per symbol, window size and modulation scheme. Results proved that BER values are improved as modulation scheme size (M) is increased. Moreover, IEEE 802.11a standards are implemented. BPSK modulation with Radix-2 FFT, OFDM transceiver design is implemented using commercial Amitec SDR04 and configured by GNU radio companion in the laboratory environment.

A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT

We present an efficient combined single-path delay commutator-feedback (SDC-SDF) radix-2 pipelined fast Fourier transform architecture, which includes log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> N - 1 SDC stages, and 1 SDF stage. The SDC processing engine is proposed to achieve 100% hardware resource utilization by sharing the common arithmetic resource in the time-multiplexed approach, including both adders and multipliers. Thus, the required number of complex multipliers is reduced to log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> N - 0.5, compared with log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> N - 1 for the other radix-2 SDC/SDF architectures. In addition, the proposed architecture requires roughly minimum number of complex adders log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> N + 1 and complex delay memory 2N + 1.5log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> N - 1.5.

High Real-Time Design of Digital Pulse Compression Based on FPGA

Because of the poor real-time performance of in-place fast Fourier transforms, a reconfigurable radix-4 FFT processor is studied and designed, which is based on decimation-in-time and single floating-point computation. The proposed method adopts “pipeline and parallel” structure for accessing multiple memories to improve the FFT processing speed, and then it is applied to digital pulse compression. The experimental result shows that the proposed FFT based on radix-4 computation can implement digital pulse compression rapidly under no adding hardware resources. The proposed method can be also applied to other radix FFTs.

Implementation of LMS-ALE Filter using Vedic Algorithm

ALE or adaptive line Enhancers are special kinds of adaptive filters widely used in noise cancellation circuits. In circuits where we don’t have any prior knowledge of signal and noise, fixed filters unit never works good. Among adaptive filter ring algorithms LMS algorithm is very common, in our work also we use LMS algorithm. LMS-ALE filters removes the sinusoidal noise signals present in the channel by calculating the filter coefficients in every iteration. LMS-ALE filter has large number of multiplier units. FFT or Fast Fourier Transform blocks present in LMS algorithm again consist of large array of multiplier units. Optimization of LMS-ALE filter lies must start from optimization of multiplier blocks. Here we use Vedic “Vertical and crosswise algorithm” for multiplier design. When compared to conventional booth multiplier based LMS-ALE filter units, Vedic multipliers gives more performance in areas like resource utilization, power requirement, delay etc. The work includes designing Vedic multipliers, complex Vedic multipliers, redesigning Radix-8 FFT using Vedic multipliers, redesigning LMS block using Vedic FFT, redesigning LMS ALE filter using Vedic multipliers and Vedic LMS blocks. Major part of design is done in Verilog using Xilinx ISE design suite. ADC block present in LMS-ALE filter is done in Matlab version 2013.

English

In this paper, our objective is to detail know-how and techniques that can help the designer of electronic circuits to develop and to optimize their own IP in a reasonable time. For this reason, we propose to optimize existing FFT algorithms for low-cost FPGA implementations. For that, we have used short length structures to obtain higher length transforms. Indeed, we can obtain a VLSI structure by using log4(N) 4-point FFTs to construct N-point FFT rather than (N/8) logs (N) 8-point FFTs. Furthermore, two techniques are used to yield with VLSI architecture. Firstly, the radix-4 FFT is modified to process one sample per clock cycle. Secondly, the memory is shared and divided into 4 parts to reduce the consumed resources and to improve the overall latency

Low Power 128 Point Split Radix FFT for LTE Application

In this paper, we describe a processor architecture customized to Split radix FFT algorithm. The proposed architecture supports all FFT sizes, required by the LTE applications. The proposed design is aimed to reduce the area, latency, power and also to reduce the number of computational path in order to speed up FFT processor computation. The proposed low power 128 point split radix FFT architecture applies various periodicity properties of twiddle factors multiplier.We implement the processor in 128-point MDC architecture with split radix algorithm. The processor has been synthesized on a Xilinx ISE 10.1design technology and both energy-efficiency and performance have been evaluated.

A Novel Architecture for Radix-4 Pipelined FFT Processor using Vedic Mathematics Algorithm

The FFT processor is a critical block in all multi-carrier systems used primarily in the mobile environment. The portability requirement of these systems is mainly responsible for the need of low power FFT architectures. In this study, an efficient addressing scheme for radix-4 64 point FFT processor is presented. It avoids the modulo-r addition in the address generation; hence, the critical path is significantly shorter than the conventional radix-4 pipelined FFT processor by modifying its operation sequence. The complex multiplier is one of the most power consuming blocks in the FFT processor. A significant property of the proposed method is that the critical path of the address generator is independent from the FFT transform length N, making it extremely efficient for large FFT transforms. The results confirm the speed and area advantages for large FFTs. Although only radix-4 FFT address generation is presented in the paper, it can be used for higher radix-4FFT.

An Implementation of Pipelined Radix-4 FFT Architecture on FPGAs

An Implementation of Pipelined Radix-4 FFT Architecture on FPGAs

Four Parallel Channels Radix-4 FFT with Single Floating-Point Butterfly

An efficient design method of four parallel channels in-order FFT with single floating-point butterfly is proposed, to reduce the resource consumption and improve the real-time calculation ability. The radix-4 FFT is deduced to calculate the access address for four channel data parallel. The hardware architecture of the proposed FFT is presented, and the single precision floating-point adder and multiplier are also depicted. The proposed architecture of a four channels 1024 points radix-4 FFT with single butterfly is implemented in FPGA, and the performance is compared with previous literatures and some EDA corporations IP cores, which shows the correctness and effectiveness of the proposed method.

Enhanced Hardware Efficient FFT Processor Based On Adaptive Recoding CORDIC

In this paper, we propose an enhanced hardware efficient CORDIC-based FFT processor. As the conventional CORDIC is restricted by the data precision and the times of iterations, Adaptive Recoding CORDIC (ARC) is adopted in our design, the bit error precision (BEP) of which is improved to 14 th . Simultaneously, Conflict-free parallel memory access scheme and Rom-free twiddle factor generation scheme are both introduced to improve the performance and reduce the memories to store the twiddle factors. Compared with some latest published FFT processors, synthesized results show the proposed FFT processor reduce the hardware overhead while improving the Signal-to-Noise Ratio (SNR). When the operating frequency is 250MHz, the proposed FFT processor performs radix-4 1024-point FFT every 5.4us. DOI: http://dx.doi.org/10.5755/j01.eee.19.4.1422

FPGA Implementation of Baseband OFDM Transmitter and Receiver Using Modified IFFT/FFT to Reduce Latency

The key component of any OFDM system is the IFFT/FFT block; moreover it is the most computationally complex block. In order to support 4G standard specified speeds, in mobile handheld devices it is necessary to reduce the computational complexity and the time taken to perform IFFT/FFT functions. The IFFT/ FFT block in the transmitter/ receiver is preceded by a serial to parallel convertor; the latency in this conversion is reduced by a novel approach. This approach presented in this paper modifies the radix-2 FFT algorithm, by evaluating the contribution by every complex input to every output on its arrival. This reduction in the latency is carried forward by allowing the outputs of IFFT/FFT block to stream out even as concurrent outputs are being calculated. In order to analyse the reduction in the complexity of the OFDM system using this approach, it is simulated for a target Xilinx device using Verilog HDL. It was observed that the device utilization was significantly reduced.

Design of a Radix-8/4/2 variable FFT processor for OFDM systems

In this paper, we propose an efficient variable-length radix-8/4/2 FFT architecture for OFDM systems. The FFT processor is based on radix-8 FFT algorithm and also supports radix-4 or radix-2 FFT computation. We are using efficient In-place memory access method to maintain conflict-free data access and minimize memory size. Also we replace a very large lookup table with a twiddle factor generator which consumes less area then a ROM-based lookup table. The proposed FFT processor performs variable-length FFT including 64, 256, 512, 1024, 2048, 4096 and 8192 points which cover all the required FFT lengths used in 802.11a, 802.16a, DAB, DVB-T, VDSL and ADSL.

Design and Implementation of FFT Module Based on Virtex Series FPGA

In order to achieve real-time data output in synthetic aperture radar (SAR) imaging system, high-speed FFT transformation is needed. In this article, we proposed the program that uses the new generation of high-speed, large-capacity Virtex series FPGA to implement radix-4 FFT algorithm and simulated it with the Modelsim software, and then through the comparative analysis of simulation results by MATLAB. After analyzing the results compared with MATLAB simulation, it shows that FFT module has stable performance, fast operation and fully meets the radar data real-time processing requirements.

Seismic Signal Wavelet-Packet Denoising and Fast Spectrum Analysis

Noise mixed in the recorded seismic signals often affects the data analysis result. To solve this problem, wavelet packet decomposition technology is selected to reduce the noise. The principle, denoising steps and algorithm of wavelet packet decomposition technology are introduced with its effectiveness and reliability verified by computer simulation. Meanwhile, split-radix FFT algorithm is used to rapidly perform spectral analysis for seismic signals. Compared with radix-2 FFT and radix-4 FFT, split-radix algorithm can significantly reduce calculation amount and improve the speed of data analysis. Field tests showed that wavelet packet denoising technology and split-radix FFT algorithm have good effect.