Abstract
In this paper, we propose an enhanced hardware efficient CORDIC-based FFT processor. As the conventional CORDIC is restricted by the data precision and the times of iterations, Adaptive Recoding CORDIC (ARC) is adopted in our design, the bit error precision (BEP) of which is improved to 14 th . Simultaneously, Conflict-free parallel memory access scheme and Rom-free twiddle factor generation scheme are both introduced to improve the performance and reduce the memories to store the twiddle factors. Compared with some latest published FFT processors, synthesized results show the proposed FFT processor reduce the hardware overhead while improving the Signal-to-Noise Ratio (SNR). When the operating frequency is 250MHz, the proposed FFT processor performs radix-4 1024-point FFT every 5.4us. DOI: http://dx.doi.org/10.5755/j01.eee.19.4.1422
Highlights
FFT processor, known as a specialized hardware, is indispensable for real-time signal processing and has been widely used in communication systems, such as WiMax [1] and 3GPP-LTE [2]
Many people have researched on FFT processor design and implementation [3]–[6], which can be classified into two styles, pipelined and memory-based architectures
We present an area-efficient pipeline-balancing coordinate rotation digital computer (CORDIC) architecture, and in 16-bit computer, the Bit Error Position (BEP) of the proposed architecture has been improved with no performance penalty
Summary
FFT processor, known as a specialized hardware, is indispensable for real-time signal processing and has been widely used in communication systems, such as WiMax [1] and 3GPP-LTE [2]. Many people have researched on FFT processor design and implementation [3]–[6], which can be classified into two styles, pipelined and memory-based architectures. Memory-based FFT processors are composed of a kernel processing unit and several memory blocks, the hardware requirement and power consumption of which are both lower than pipelined FFT processors [5], [6], and we adopt the memory-based FFT in our work. One complex multiplier needs four real multipliers and two adders, the butterfly units are the speed bottleneck in FFT processor. We present an area-efficient pipeline-balancing CORDIC architecture, and in 16-bit computer, the Bit Error Position (BEP) of the proposed architecture has been improved with no performance penalty.
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