VLSI Design of a Hardware Efficient FFT Processor

Abstract

This paper presents a CORDIC-based radix-4 FFT processor, which adopts an improved conflict-free parallel memory access scheme and the pipelined CORDIC architecture. By generating the twiddle factor correctly, the proposed FFT processor eliminates the need of ROM making it memory-efficient. Synthesis results show that the 16-bit 1024-point FFT processor only has 45 K equivalent gates with area of 0.13 mm2 excluding memories in Chartered 90 nm CMOS technology. When the operating frequency is 350 MHz, the proposed FFT processor performs 1024-point FFT every 3.94 μs.