Radio Frequency Integrated Circuit Applications Research Articles

A novel source material engineered double gate tunnel field effect transistor for radio frequency integrated circuit applications

Tunnel field effect transistors (TFETs) have proved their potential for many possible electronic circuit applications. However, with the variety of TFET structures being worked upon it has been an unresolved challenge to optimize them for the applications to which they are best suited. In this paper we present a detailed comparative analysis of the linearity distortion and the radiofrequency (RF) performance parameters of a proposed heterojunction Mg2Si source double gate TFET (HMSDG-TFET) and a conventional homojunction Si source DG-TFET (SSDG-TFET). A source material engineering scheme is utilized to implement a staggered type 2 heterojunction at the source–channel junction by replacing the source material with Mg2Si (a low band gap material) to enhance the ON current (2.5 × 10–4 A µm−1), reduce the threshold voltage (0.26 V) and achieve a steeper subthreshold swing (10.05 mV decade−1). For linearity and distortion analysis, the figure of merit (FOM)-like higher-order transconductances, second- and third-order voltage intercepts, third-order intercept point, third-order intermodulation distortion, zero crossover point, 1 dB compression point, second-order harmonic distortion, third order harmonic distortion and total harmonic distortion have been examined. To portray the possible application of devices under consideration for RF integrated circuit applications, both structures are investigated for RF FOMs such as power gains, cutoff frequency (fT), maximum oscillation frequency (F max) and admittance parameters. Investigations carried out using a Silvaco ATLAS device simulator tool revealed that with fT approximately three orders higher (0.49 THz) and F max approximately two orders higher (0.9 THz) than that of a SSDG-TFET, the HMSDG-TFET is an appropriate candidate for use in high-frequency, high-linearity, low-distortion and low-power analog/RF applications.

Quality factor enhancement techniques for inductor and transformer

ABSTRACTQuality factor enhancement for inductor and transformer has been achieved by the techniques such as fabricating the inductor and transformer on a glass substrate having high resistivity and by fabricating the inductor far away the silicon substrate and within this distance use of air, high-resistive silicon and silicon nitride as cavity. The simulation results are obtained by using the tool ASITIC (analysis and simulation of inductor and transformer for integrated circuits). Inductor is a key component in radio frequency (RF)-based devices and shows poor RF characteristics when it is formed on a Si substrate chip. It happens because of substrate-based RF losses and parasitics arised due to inter spiral tracks. Fabrication of inductor and transformer on a glass substrate results in a high quality factor as well as high self-resonance frequency which shows good prospects in various radio frequency integrated circuits applications.

TIME—Tunable Inductors Using MEmristors

Memristors have proven to be an attractive feature for memory, logic-in-memory, and neuromorphic computing. Recently, radio-frequency memristive switches (RFMSs) have exhibited promising high-frequency performance, opening the possibility of their use in radio-frequency integrated circuit applications. In this paper, we present two novel topologies of Tunable Inductors using MEmristors, the memristive–via the switched tunable inductor and the multi-layer stacked inductor switched by an RFMS single-pole double-throw. The two inductor topologies are fully passive and are tuned by electrochemical metallization memristors. Memristive devices improve the performance of tunable inductors, as they provide low-area overhead, low-energy switching, and non-volatility, resulting in more compact and energy-efficient devices. The topologies are implemented and simulated in a momentum 3-D planar electromagnetic simulator. Simulation results show a maximum tunability of 296%, a quality factor of 18 at 5 GHz, and self-resonant frequency above 8.4 GHz.

Fractal series stacked inductor for radio frequency integrated circuit applications

High-quality factor miniaturised inductors are prerequisites of radio frequency integrated circuit applications. This Letter presents a novel fractal stacked inductor using modified Hilbert space filling curve. The proposed inductor achieves higher inductance value and good quality factor because of mutual inductance between plural metal layers and the reduced parasitic resistance. The results show that more than double improvement in L over conventional fractal inductors and more than double improvement in quality factor value over conventional series stack construction.

Publisher's Note: “High quality factor integrated gigahertz magnetic transformers with FeGaB/Al2O3 multilayer films for radio frequency integrated circuits applications” [J. Appl. Phys. 115, 17E714 (2014)

Publisher's Note: “High quality factor integrated gigahertz magnetic transformers with FeGaB/Al2O3 multilayer films for radio frequency integrated circuits applications” [J. Appl. Phys. <b>115</b>, 17E714 (2014)

High quality factor integrated gigahertz magnetic transformers with FeGaB/Al2O3 multilayer films for radio frequency integrated circuits applications

This work report new integrated high quality factor (Q) GHz magnetic transformers based on solenoid structures with FeGaB/Al2O3 multilayer films. These transformers show excellent high-frequency performance with a wide operation frequency range of 0.5–5 GHz, in which primary, secondary, and mutual inductances are flat, and the peak quality factor can reach around 14 at frequency of 1.2 GHz. High mutual coupling and low insertion loss are also demonstrated. These novel GHz transformers with high Q and mutual coupling show great promise for applications in radio frequency integrated circuits.

Development of a MEMS/IC Design Environment for RFIC Applications

The development of MEMS/IC design environment based on SMIC 0.13um CMOS process was reported. This effort includes the development of PDK (Process Design Kit) by integrating MEMS inductor devices. The MEMS inductors can be used to design high performance RF circuit with standard CMOS devices. A low noise amplifier (LNA) circuit was designed with the PDK. The results showed that the MEMS inductors can improve the performance of the LNA circuit and the PDK can be used for Radio Frequency Integrated Circuits (RFIC) design. This work has laid a foundation for our future development of a design environment for MEMS/IC applications.

Rotational Driven RF Variable Capacitors With Post-CMOS Processes

A ring-shaped on-chip tunable capacitor is proposed and fabricated with CMOS-compatible micromachining processes for radio frequency integrated circuits (RFICs). The rotationally driven variable capacitor features a much higher axial mechanical stiffness compared to its conventional straight-line-driven counterpart, and therefore, can effectively depress the instability caused by environmental vibration when the varactor is used in mobile systems. Meanwhile, the rotationally driven intedigitated capacitor is designed to be very flexible for wide range of electrostatic tuning. Near-room-temperature micromachining techniques are developed for post-CMOS integrating the tunable capacitors into RFIC chips. The fabricated varactor is measured with a tuning ratio of 2.1:1 under an actuation of 12 V. Q-factor is measured as 51.3 at 1 GHz and 35.2 at 2 GHz, while self-resonance frequency is as high as 9.5 GHz. The rotationally driven tunable capacitor shows about two orders of magnitude higher antivibration capability compared to the conventional straight-driven one. Therefore, the high-performance CMOS-compatible tunable capacitors are promising for practical RFIC applications in mobile electronic telecom systems.

Design of On-Chip Transformer With Various Coil Widths to Achieve Minimal Metal Resistance

A layout design algorithm of a variable-width transformer is proposed to minimize metal resistance in this letter. The proposed algorithm can rapidly design metal widths in each coil of a planar transformer for a given chip area. Two on-chip transformers with identical self-inductance are fabricated to verify the proposed algorithm in 90-nm CMOS technology. Measurement results demonstrate the improvement of metal resistance approximates to the value of 11.6%. Results of this study provide an effective algorithm to design a minimal-loss transformer for radio frequency integrated circuit applications.

Concave-Suspended High-$Q$ Solenoid Inductors With an RFIC-Compatible Bulk-Micromachining Technology

Presented in this brief is a concave-suspended solenoid inductor that can be post-CMOS integrated into a low-resistivity silicon substrate using a novel radio frequency integrated circuit (RFIC)-compatible micromachining technology. The three-mask processes include photoresist spray coating, XeF2 gaseous etching and copper electroplating, etc. The fabricated 11.5-turn inductor is measured with 2.96-nH inductance at 5.35 GHz, where the peak Q-factor is as high as about 45. Even with a compact layout (50% area occupation saved), the 8.5-turn inductor is still measured with 2.78 nH and peak Q of about 28 at 4.90 GHz. Both finite element simulation and shock testing results show that the suspended inductor is almost free of influence from environmental vibration and shock. Featuring high-Q performance and robust properties, the RFIC-compatible inductors are promising for high-performance RFIC applications

An Analysis of Perfect-Magnetic-Coupling Ultra-Low-Loss Micromachined SMIS RF Transformers for RFIC Applications

Selective removal of the silicon underneath a set of single-turn multilayer interlaced stacked (SMIS) radio-frequency (RF) transformers with nearly perfect magnetic-coupling factor (k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IM</sub> ~1) and high resistive-coupling factor (k <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Re</sub> ) is demonstrated. This process is based on the inductively coupled-plasma (ICP) deep trench technology. Improvement of 20.6 and 15.7 dB in isolation (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> ) were achieved at 5.2 and 8 GHz, respectively, for a dummy open device after the backside ICP etching. Q-factor increases of 102% (from 4.96 to 10.03) and 23.2% (from 2.24 to 2.76), G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> increases of 11.8% (from 0.76 to 0.85) and 4.5% (from 0.88 to 0.92), and NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min </sub> decreases of 0.49 dB (from 1.22 to 0.73 dB) and 0.19 dB (from 0.55 to 0.36 dB) were achieved at 5.2 and 8 GHz, respectively, for an SMIS transformer with an overall dimension of 170times240 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sup> after the backside ICP etching. The G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> of 0.85 and 0.92 are both state-of-the-art results among all reported on-chip transformers. Furthermore, the reasons why the SMIS transformer exhibits better performances than the traditional bifilar and the traditional stacked transformer are explained. These results show that the micromachined SMIS transformers are very promising for RF integrated circuit applications

A high quality factor and low power loss micromachined RF bifilar transformer for UWB RFIC applications

In this letter, the authors demonstrate that high quality factor and low power loss transformers can be obtained by using the CMOS process-compatible backside inductively coupled plasma (ICP) deep-trench technology to selectively remove the silicon underneath the transformers. A 62.4% (from 8.99 to 14.6) and a 205.8% (from 8.6 to 26.3) increase in the Q-factor, a 10.3% (from 0.697 to 0.769) and a 30.2% (from 0.652 to 0.849) increase in the maximum available power gain (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> ), and a 0.43- (from 1.57 to 1.14 dB) and a 1.15-dB (from 1.86 to 0.71 dB) reduction in the minimum noise figure (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min </sub> ) were achieved at 5.2 and 10 GHz, respectively, for a bifilar transformer with overall dimension of 240times240 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> after the backside ICP etching. The values of G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> of 0.769 and 0.849 are both state-of-the-art results among all reported on-chip bifilar transformers. These results indicate that the backside ICP deep-trench technology is very promising for high-performance radio frequency integrated circuit applications

SOI technology for radio-frequency integrated-circuit applications

This paper presents a silicon-on-insulator (SOI) integration technology, including structures and processes of OFF-gate power nMOSFETs, conventional lightly doped drain (LDD) nMOSFETs, and spiral inductors for radio frequency integrated circuit (RFIC) applications. In order to improve the performance of these integrated devices, body contact under the source (to suppress floating-body effects) and salicide (to reduce series resistance) techniques were developed for transistors; additionally, locally thickened oxide (to suppress substrate coupling) and ultra-thick aluminum up to 6 /spl mu/m (to reduce spiral resistance) were also implemented for spiral inductors on high-resistivity SOI substrate. All these approaches are fully compatible with the conventional CMOS processes, demonstrating devices with excellent performance in this paper: 0.25-/spl mu/m gate-length offset-gate power nMOSFET with breakdown voltage (BV/sub DS/) /spl sim/ 22.0 V, cutoff frequency (f/sub T/)/spl sim/15.2 GHz, and maximal oscillation frequency (f/sub max/)/spl sim/8.7 GHz; 0.25-/spl mu/m gate-length LDD nMOSFET with saturation current (I/sub DS/)/spl sim/390 /spl mu/A//spl mu/m, saturation transconductance (g/sub m/)/spl sim/197 /spl mu/S//spl mu/m, cutoff frequency /spl sim/ 25.6 GHz, and maximal oscillation frequency /spl sim/ 31.4 GHz; 2/5/9/10-nH inductors with maximal quality factors (Q/sub max/) 16.3/13.1/8.95/8.59 and self-resonance frequencies (f/sub sr/) 17.2/17.7/6.5/5.8 GHz, respectively. These devices are potentially feasible for RFIC applications.

A New Modeling Technique for Simulating 3-D Arbitrary Conductor-Magnet Structures for RFIC Applications

This paper presents a new modeling technique, entitled extended MagPEEC model, which can be used to simulate arbitrary three-dimensional conductor-magnet structures of any geometry with direct conductor-magnet interfaces included. The new model was validated using a sample coaxial transmission line structure and was applied to investigate a group of super compact six-layer stacked spiral radio frequency integrated circuits (RFICs) inductor structures with various magnetic media integrated inside. This new modeling technique can be used to assist design of complex conductor-magnet structures including various magnetic-enhanced inductors for RFIC applications.

A Robust High-&amp;lt;tex&amp;gt;$Q$&amp;lt;/tex&amp;gt;Micromachined RF Inductor for RFIC Applications

In this paper, a robust micromachined spiral inductor with a cross-shaped sandwich membrane support is proposed and fabricated with fully CMOS compatible post-processes for radio frequency integrated circuit (RFIC) applications. Using the incorporation of a sandwich dielectric membrane (0.7 /spl mu/m SiO/sub 2//0.7 /spl mu/m Si/sub 3/N/sub 4//0.7 /spl mu/m TEOS) to enhance the structure rigidity, the inductor can have better signal stability. In comparison, the new design of a /spl sim/5-nH micromachined inductor can have 45% less inductance variation than the one without the dielectric support while both devices are operated with 10 m/s/sup 2/ acceleration. Meanwhile, using a cross shape instead of blanket membrane can also effectively eliminate the inductance variation induced by the working temperature change (20/spl deg/C to 75/spl deg/C). The measurement results show the robust inductor can have similar electrical performance to the as-fabricated freely suspended inductor, which has five times Q (quality factor) improvement than the inductor without the substrate removal. It is our belief that the new micromachined inductors can have not only high-Q performance but also better signal stability suitable for wide-range RFIC applications.

Improved performance of Si-based spiral inductors

Conventional spiral inductors on silicon wafer have suffered low quality (Q) factor due to substrate loss. In this work, a technique that combines optimized shielding poly and proton implantation treatment is utilized to improve inductor Q-value. The optimized poly-silicon and proton-bombarded substrate have added 37% and 54% increment to the Q-value of inductors, respectively. If two techniques are combined, a phenomenal Q-value increment as high as 122% of 4-nH spiral inductors can be realized. The combination of the two means has created a multiplication of their individual contribution rather than addition. The technique used in this work shall become a critical measure to put inductors on silicon substrate with satisfactory performance for Si-based radio frequency integrated circuit applications.