Abstract
In this letter, the authors demonstrate that high quality factor and low power loss transformers can be obtained by using the CMOS process-compatible backside inductively coupled plasma (ICP) deep-trench technology to selectively remove the silicon underneath the transformers. A 62.4% (from 8.99 to 14.6) and a 205.8% (from 8.6 to 26.3) increase in the Q-factor, a 10.3% (from 0.697 to 0.769) and a 30.2% (from 0.652 to 0.849) increase in the maximum available power gain (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> ), and a 0.43- (from 1.57 to 1.14 dB) and a 1.15-dB (from 1.86 to 0.71 dB) reduction in the minimum noise figure (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min </sub> ) were achieved at 5.2 and 10 GHz, respectively, for a bifilar transformer with overall dimension of 240times240 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> after the backside ICP etching. The values of G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Amax</sub> of 0.769 and 0.849 are both state-of-the-art results among all reported on-chip bifilar transformers. These results indicate that the backside ICP deep-trench technology is very promising for high-performance radio frequency integrated circuit applications
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