Quiescent Current Consumption Research Articles

A 600-mA Multifeedback Loop Capacitorless Low-Dropout Regulator With a –40-dB Power Supply Rejection at 1 MHz With 27.5-μA Quiescent Current Consumption

A 600-mA Multifeedback Loop Capacitorless Low-Dropout Regulator With a –40-dB Power Supply Rejection at 1 MHz With 27.5-μA Quiescent Current Consumption

A 99.99% current efficiency fast transient response capacitor-less LDO with feedforward compensation technique based on small-signal gain stage

An ultra-low power capacitor-less LDO with feedforward compensation technique based on the small-signal gain stage and composite transient enhancement structure is proposed. The feedforward compensation technique based on the small-signal gain stage reaches a low frequency zero ,by utilizing the compensating effect of the zero to relieve the adverse effects of the pole, thereby enhancing the stability and performance of the circuit. Furthermore, the small gain stage can adjust the quiescent current consumption,contributing to a significant reduction in system energy consumption. The proposed composite transient enhancement structure can reduce the transition time of the circuit, adjust the gain of the circuit under different operating conditions to achieve precise gain control and improve the transient performance of the system. The proposed LDO is designed using SMIC 0.18um CMOS process. The simulation results show the total quiescent current is 0.94uA and the current efficiency is up to 99.99%. The extremely low FoM value of 0.04 represents a good transient performance. Synthesizing the comparison of various parameters, the superiority of this design can be clearly concluded.

A low dropout regulator design with 20.4 μA quiescent current and high power supply rejection

This paper presents a novel low dropout (LDO) regulator distinguished by its high power supply rejection (PSR) and low quiescent current. A capacitive feed-forward ripple cancellation (CFFRC) technique is introduced to effectively cancel power supply noise while simultaneously minimizing quiescent current. Additionally, the design incorporates feed-forward capacitors and back-to-back pseudo-resistors biasing to achieve reduced power consumption. Furthermore, the integration of negative feedback super source follower and Miller compensation techniques enhances the stability of the LDO. Fabricated using 180 nm CMOS technology, the LDO exhibits a quiescent current consumption of 20.4 μA. Experimental results demonstrate a maximal improvement of −41.55 dB in PSR compared to an LDO lacking these enhancements, with a maximum load current capability of 120 mA.

A high PSR and high-precision current-mode bandgap reference with gm boost self-regulated structure

A high power supply rejection and high-precision current-mode bandgap reference system with a reliable start-up gm boost self-regulated structure is presented in this paper. The gm boost technology and high-precision compensation structure are adopted to improve the power supply rejection and precision of the output reference current, respectively. The proposed reference system has been designed in Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The simulation results show that with a supply voltage of 3.3 V, the power supply rejection is −101.3dB@DC, −60.23dB@1MHz and −55.6dB@10MHz, the temperature coefficient of the output reference current of proposed circuit is approximately 3.14 ppm/°C in a temperature range from −40 to 125 °C, the quiescent current consumption is 47.8 μA and the silicon area is 0.0992 mm2.

A High-Precision Current-Mode Bandgap Reference with Nonlinear Temperature Compensation.

A high-precision current-mode bandgap reference (BGR) circuit with a high-order temperature compensation is presented in this paper. In order to achieve a high-precision BGR circuit, the equation of the nonlinear current has been modified and the high-order term of the current flowing into the nonlinear compensation bipolar junction transistor (NLCBJT) is compensated further. According to the modified equation, two solutions are designed to improve the output accuracy of BGR circuits. The first solution is to divide the NLCBJT branch into two branches to reduce the coefficient of the nonlinear temperature compensation current. The second solution is to inject the nonlinear current into the two branches based on the first one to further eliminate the temperature coefficient (TC) of the current flowing into the NLCBJT. The proposed BGR circuit has been designed using the Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The simulation results show that the variations in currents flowing into NLCBJTs improved from 148.41 nA to 69.35 nA and 7.4 nA, respectively, the TC of the output reference current of the proposed circuit is approximately 3.78 ppm/°C at a temperature range of -50 °C to 120 °C with a supply voltage of 3.3 V, the quiescent current consumption of the entire BGR circuit is 42.13 μA, and the size of the BGR layout is 0.044 mm2, leading to the development of a high-precision BGR circuit.

Design of a Wide Input Voltage Low Quiescent Current LDO

A low-dropout linear regulator (LDO) with wide input voltage range, wide output voltage range and low quiescent current power consumption is proposed, which is applied to the switching power supply chip to power the internal module of the switching power supply chip. The low-dropout linear regulator is based on a P-type PowerFET design consisting of an error amplifier, a Bandgap reference. The circuit was designed and implemented by SMIC 0.18um BCD process, simulated and verified using Spectre software. The simulation results show that the linear regulation is 0.04mV/V in the input voltage range of 3.5-30V, and the load regulation is 1mV/mA in the output load current range of 10uA to 10mA, and the quiescent current is only 10uA.

A high-efficiency feedforward compensation method for capacitor-less LDO

This paper proposes a new structure of compensation for LDO. A feedforward path is added to this system and the gain of this feedforward stage is well-controlled by using the proposed structure so that it can accurately change the position of the zero generated by this system for accurate frequency compensation. The structure substantially improves stability at low power consumption, so that this structure implements a high-efficiency compensation method. This LDO is under SMIC 0.18μm CMOS process with a total area of 0.031 mm2. When the load current is 20 mA, the line regulation can be as low as 0.33 mV/V. The phase margin of proposed LDO can reach around 90 deg and the recovery time is less than 2μs. It is worth mentioning that the total quiescent current consumption of proposed LDO is only 6.58 μA and the current efficiency is above 99.94%.

An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing

This brief presents an ultra-low power low-dropout (LDO) regulator with an experimental total quiescent current consumption of only 3.08 nA. The circuit is designed to operate with a load current in the range 0 - 11 mA. A novel adaptive biasing scheme based on a super source follower (SSF) structure is proposed, which measures the absolute voltage difference between the two inputs of the LDO’s error amplifier and modifies the biasing current accordingly. Thus, the transient response of the regulator is improved by counteracting the effect of using such a low bias current. The proposed LDO has been fabricated in a standard CMOS 180 nm process and the experimental characterization showed an outstanding performance in terms of maximum load current over quiescent current consumption ratio.

A Low-Power, Fast-Transient Output-Capacitorless LDO with Transient Enhancement Unit and Current Booster

With the wide application of advanced portable devices, output-capacitorless low dropout regulators (OCL-LDO) are receiving increasing attention. This paper presents a low quiescent current OCL-LDO with fast transient response. A transient enhancement unit (TEU) is proposed as the output voltage-spike detection circuit. It enhances the transient response by improving the slew-rate at the gate of the power transistor. In addition, a current booster (CB), which consists of a current subtractor and a non-linear current mirror, is designed to improve the slew-rate further. The current subtractor increases the transconductances of the differential-input transistors to obtain a large slewing current, while the non-linear current mirror further boosts the current with no extra quiescent current consumption. The simulated results show that the proposed OCL-LDO is capable of supplying 100 mA load current while consuming 10.3 μA quiescent current. It regulates the output at 1 V from a supply voltage ranging from 1.2 to 1.8 V. When the load current is stepped from 1 mA to 100 mA in 100 ns, the OCL-LDO has attained a settling time of 190 ns, and the output voltage undershoot and overshoot are controlled under 110 mV.

A 0.4-mA-Quiescent-Current, 0.00091%-THD+N Class-D Audio Amplifier With Low-Complexity Frequency Equalization for PWM-Residual- Aliasing Reduction

This article proposes a low-complexity frequency equalization technique for pulsewidth modulation (PWM)-residual-aliasing reduction in closed-loop Class-D audio amplifiers to achieve both low total harmonic distortion plus noise (THD+N) and low quiescent current. Based on the comprehensive analysis on the phase shift delay between the audio input and the loop filter’s output for the prior PWM-residual-aliasing reduction technique, the proposed technique minimizes the non-idealities via a frequency-equalization path to enhance the cancellation ability of high-frequency PWM switching components. In this way, the PWM-residual-aliasing distortion is greatly suppressed, thereby permitting Class-D audio amplifiers to achieve a further-reduced THD+N for the entire audio band while operating at a low switching frequency ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm {SW}}$ </tex-math></inline-formula> ), leading to less quiescent current consumption. Moreover, due to the minimized phase shift delay, the required bias current of the loop filter’s first operational amplifier for the target THD+N can be reduced, resulting in even lower quiescent current. Compared with other state of the arts, this work’s high-fidelity second-order Class-D audio amplifier, fabricated with cost-efficient 0.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology, not only achieves a competitive minimal THD+N of 0.00091% for a 1-kHz input as well as the lowest maximal THD+N of 0.0027% over the entire audio band while operating at a low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm {SW}}$ </tex-math></inline-formula> of 168 kHz but also features both the highest figure of merit (FOM) of 2536 and the lowest quiescent current of 0.4 mA, surpassing the prior arts by a factor of 2.3.

A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled Buck Converter With A2-Comparator and Sleep-Time Detector for IoT Application

An ultralow-quiescent current dc-dc buck converter with a single controller is presented to achieve high efficiency over a wide load range for Internet of Things application, which is achieved by utilizing adaptive on-time control topology. An on-demand modulation strategy and sleep-time detector are proposed to attain sub-μA quiescent current consumption under ultralight load condition. The adaptive-bias and adaptive-gain (A <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) comparator is presented to improve the loop stability caused by the inherent propagation delay of the low-power comparator. Moreover, a novel on-time generator is proposed to fix the switching frequency in continuous conduction mode. The proposed buck converter was implemented by using a 0.18-μm CMOS process with an area of 1.092 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It achieves a peak efficiency of 95.8% and >90% efficiency from 10 μA to 300 mA. A 240-nA quiescent current, including bandgap voltage and current reference, is achieved. With a low output ripple of less than 20 mV, the input voltage range and regulated output voltage are 2.1-5.5 and 1.8 V, respectively.

A Low-Power CMOS Bandgap Voltage Reference for Supply Voltages Down to 0.5 V

A voltage reference is strictly required for sensor interfaces that need to perform nonratiometric data acquisition. In this work, a voltage reference capable of working with supply voltages down to 0.5 V is presented. The voltage reference was based on a classic CMOS bandgap core, properly modified to be compatible with low-threshold or zero-threshold MOSFETs. The advantages of the proposed circuit are illustrated with theoretical analysis and supported by numerical simulations. The core was combined with a recently proposed switched capacitor, inverter-like integrator implementing offset cancellation and low-frequency noise reduction techniques. Experimental results performed on a prototype designed and fabricated using a commercial 0.18 μm CMOS process are presented. The prototype produces a reference voltage of 220 mV with a temperature sensitivity of 45 ppm/°C across a 10–50 °C temperature range. The proposed voltage reference can be used to source currents up to 100 μA with a quiescent current consumption of only 630 nA.

High-Frequency Low-Current Second-Order Bandpass Active Filter Topology and Its Design in 28-nm FD-SOI CMOS

Fully Depleted Silicon on Insulator (FD-SOI) CMOS technology offers the possibility of circuit performance optimization with reduction of both topology complexity and power consumption. These advantages are fully exploited in this paper in order to develop a new topology of active continuous-time second-order bandpass filter with maximum resonant frequency in the range of 1 GHz and wide electrically tunable quality factor requiring a very limited quiescent current consumption below 10 μA. Preliminary simulations that were carried out using the 28-nm FD-SOI technology from STMicroelectronics show that the designed example can operate up to 1.3 GHz of resonant frequency with tunable Q ranging from 90 to 370, while only requiring 6 μA standby current under 1-V supply.

A 0.18 μm CMOS capacitor-less Low-Drop Out Voltage Regulator Compensated via the Bootstrap Flipped-Voltage Follower

This work presents a Cap-less Low-Drop Out (LDO) Voltage Regulator that uses a Bootstrap Flipped-Voltage Follower (B-FVF) as the input stage of its active compensation network. Previous works use active compensation networks whose frequency response shows a high-pass behavior that depends on their compensation capacitor Cf. The dominant pole is related to the value of Cf. By using the B-FVF, this Cf-pole dependency is broken; only the gain of the compensation loop lies on Cf, while the high-pass pole is referred to the B-FVF input node capacitance. This advantage allows the integration of a smaller Cf, a 10X reduction compared with the state-of-the-art, and easier placement of the high-pass pole to higher frequencies than the LDO open-loop Gain Bandwidth (GBW). The proposed LDO presents a quiescent current consumption of 95 μA at a 1.8 V input voltage, delivering a 0mA–50mA load current at a 1.6 V output voltage. A load and line transient responses of 133 mV and 165 mV were measured by using a Cf of only 0.3 pF and a load capacitor CL of 100 pF. In order to validate the proposed LDO, simulations and measurements were performed in 0.18 μm CMOS Standard technology. The silicon area consumption is 0.133 mm2.

Design of High Speed and Precision and Low-Power LVDS Driver for CMOS Image Sensor

Aiming at the requirement of high speed and precision, low-power and large-capacity load of serial data interface for aerospace super large array(15k×15k) CMOS image sensor, a design scheme low voltage differential signal (LVDS) driver by combining the split-length method with the pre-emphasis technique is proposed. Firstly, comparing with the general design schemes, the present scheme uses the split-length compensation method to increase effectively the unity-gain bandwidth while keeping the op-amp gain constant. Secondly, the pre-emphasis technique is used to compensate the LVDS driver for high-frequency components to improve the driving capability of the capacitive load and high speed signal integrity (SI). The simulation results show that the accuracy of the common-mode feedback voltage is improved by using the split-length compensation method, and also the common-mode voltage changes below 15 mV. The pre-emphasis technique is used to enhance the amplitude of the high-frequency components lost during the high-speed transmission. The quality of the signal eye diagram during high-speed transmission reduces the bit error rate, and both the transmission rate and the driving load capacity are two times more than the general design (1.2 Gb/s@12 pF), and the quiescent current consumption is only 4.6 mA@12 pF. The present LVDS driver design is implemented in a typical CMOS process of 0.18 μm.

Fast transient low‐dropout regulator with undershoot and settling time reduction technique

This article proposes an external capacitor-less low-dropout (LDO) regulator with undershoot and settling time reduction technique for fast transient response. In the proposed LDO, a feedback capacitor is applied instead of a complicated voltage-spike detection circuit to reduce undershoot voltage and settling time without consuming additional quiescent current. When an undershoot or overshoot voltage occurs in the load transient response, the undershoot voltage and settling time are reduced by increasing the gate discharging current or gate charging current of the pass transistor by the current flowing through the feedback capacitor. An adaptively biased single-stage error amplifier with a cross-coupled pair is used to improve stability without external capacitors at low quiescent current consumption. The proposed LDO regulator is implemented with a 0.18 μm CMOS process and consumes a quiescent current of 3.0 μA at a minimum load current of 0.1 mA. Compared with the conventional LDO regulator, the proposed LDO regulator reduces the undershoot voltage by 53.3% and the settling time by 55.5% without consuming additional quiescent current.

An ultra low-voltage rail-to-rail comparator for on-chip energy harvesters

This paper presents a performance evaluation of an ultra low-voltage non-clocked voltage comparator, designed and fabricated in a standard twin-well 130 nm CMOS technology. The comparator can handle the input voltage within rail-to-rail range and is capable of working in temperature range from −20 to 85 °C and with power supply voltage as low as 0.4 V. The comparator is intended to be employed in an on-chip energy harvester system with minimized quiescent current consumption. So-called gm/ID low-voltage design methodology in combination with the bulk-driven design approach have been selected in the circuit topology. The measurement results obtained from fabricated prototype chips, including static and dynamic parameters, are presented and discussed as well. An excellent correlation between simulations and the measured bench data has been observed with the supply voltage value of 0.6 V, while slightly less tight correlation has been reported for VDD = 0.4 V. Anyhow, simulations and measurements both confirm that the presented silicon-proven comparator topology is capable of reliable operation with power consumption within nW range.

A Fully Integrated Bluetooth Low-Energy Transceiver with Integrated Single Pole Double Throw and Power Management Unit for IoT Sensors.

This paper presents a low power Gaussian Frequency-Shift Keying (GFSK) transceiver (TRX) with high efficiency power management unit and integrated Single-Pole Double-Throw switch for Bluetooth low energy application. Receiver (RX) is implemented with the RF front-end with an inductor-less low-noise transconductance amplifier and 25% duty-cycle current-driven passive mixers, and low-IF baseband analog with a complex Band Pass Filter(BPF). A transmitter (TX) employs an analog phase-locked loop (PLL) with one-point GFSK modulation and class-D digital Power Amplifier (PA) to reduce current consumption. In the analog PLL, low power Voltage Controlled Oscillator (VCO) is designed and the automatic bandwidth calibration is proposed to optimize bandwidth, settling time, and phase noise by adjusting the charge pump current, VCO gain, and resistor and capacitor values of the loop filter. The Analog Digital Converter (ADC) adopts straightforward architecture to reduce current consumption. The DC-DC buck converter operates by automatically selecting an optimum mode among triple modes, Pulse Width Modulation (PWM), Pulse Frequency Modulation (PFM), and retention, depending on load current. The TRX is implemented using 1P6M 55-nm Complementary Metal–Oxide–Semiconductor (CMOS) technology and the die area is 1.79 mm2. TRX consumes 5 mW on RX and 6 mW on the TX when PA is 0-dBm. Measured sensitivity of RX is −95 dBm at 2.44 GHz. Efficiency of the DC-DC buck converter is over 89% when the load current is higher than 2.5 mA in the PWM mode. Quiescent current consumption is 400 nA from a supply voltage of 3 V in the retention mode.

High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;${C}_{L}$ &lt;/tex-math&gt; &lt;/inline-formula&gt;

This brief presents a low-power, area-efficient three-stage CMOS operational transconductance amplifier (OTA) suitable for very large capacitive loads, C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> . A single Miller capacitor and an inverting current buffer embedded in the input stage are exploited to implement the frequency compensation network. An additional feed-forward path and a slew rate enhancer are also utilized to improve the large-signal transient response. Detailed small-signal analysis reveals that the proposed OTA does not exhibit an upper limit of drivable C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> . The OTA is fabricated in a standard 0.35-μm technology and occupies 0.0027 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of die area. Under 1.4-V supply and 6.36-μA quiescent current consumption, it provides a dc gain greater than 110 dB and is stable for any C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> larger than 5 nF. Comparison with the state of the art shows remarkable improvement of both small- and large-signal performance.

Design Space Exploration of Distributed On-Chip Voltage Regulation Under Stability Constraint

Integrating multiple on-chip voltage regulators in a power delivery network (PDN) can offer promising improvements in both voltage regulation and power efficiency. However, the complex interactions between active regulators and the surrounding parasitic passive network create a large number of feedback loops and thus cause stability concern for the distributed regulation network. The recently emerged PDN design methodology based on the hybrid stability theory (HST) provides a unique opportunity for taming the complex PDN stability problem. However, the HST-based stability margin is unfamiliar to circuit designers, and therefore stability-constrained design intuitions are derivable. In this brief, our systematic analysis reveals unique design considerations which can significantly impact the system-level stability and performances. Within a large design space, a comprehensive set of design studies are conducted to shed light on the tradeoffs between the HST-based stability margin and other PDN design specifications such as the quiescent current consumption, maximum switching noise, and area overhead. Useful design insights like how regulator topology, passive decoupling capacitance, and the number of on-chip regulators may be optimized for improved tradeoffs between stability and system performance are discussed. These insights can aid circuit designers to make appropriate design choices at the beginning of the design process for improved system tradeoffs.