Quasi-floating Gate Research Articles

A bulk-driven quasi-floating gate FVF current mirror for low voltage, low power applications

This paper introduces a new low-voltage, low-power FVF current mirror circuit. The bulk-driven (BD) technique is employed to achieve extended input voltage swing and low supply voltage. Besides, the quasi-floating gate (QFG) is used to achieve high frequency performance. The merging of (BD) and (QFG) appear as a good and attractive solution to improve the circuit performance with reduced supply voltage. Benefiting from the interesting properties of (BD-QFG) MOSFET (MOST) technique, the proposed FVF current mirror circuit exhibits superior performance compared to other previously reported works. The workability of the proposed circuit has been verified through ELDO simulator based on a 0.18 μm USMC process. It achieves an enhanced bandwidth (2.7 GHz), low power consumption (79.33 μW), a low input impedance (130 Ω), and high output impedance (9.5 G Ω) from a low supply voltage (0.8 V). Monte Carlo simulation is also carried out, which proves the robust performance of the proposed circuit against mismatches. An application of the proposed current mirror is presented in the form of the current comparator to ensure the workability of the proposed BD-QFG current mirror.

A 1.1 μW biopotential amplifier based on bulk-driven quasi-floating gate technique with extremely low-value of offset voltage

Biopotential amplifier (BPA) remains one of the most crucial blocks for the successful implementation of any of the biomedical systems. However, design of a BPA remains challenging owing to most of the topologies reported in literature displaying high values of noise, consuming high value of power and working in limited range of bandwidth. Thus, circuit topologies capable of providing an optimum and an acceptable combination of these parameters remains a topic of immense interest among researchers. We in this paper, report the results of a BPA designed using Bulk-Driven Quasi-Floating Gate (BDQFG) technique with a special focus on the effect of variation in the values of biasing resistor (Rlarge). Results obtained through mathematical modelling and analysis of the circuit have been verified by conducting simulations in Cadence Analog Design Environment using standard 0.18 µm technology. Circuit design has been optimized for least values of power consumption of the order of 1.1 µW, noise (≈ 3.15 µVRMS), mid-band gain of 39.9 dB (from 0.266 Hz to f-3dB of 2.8 kHz), offset voltage of 455 μV and phase margin of 65.83°.

Analog Building Blocks Using QFGMOS Technique

In this paper, quasi-floating gate MOSFET (QFGMOS) based current divider and pseudo-exponential function generator circuits are proposed. The use of QFGMOS makes the proposed circuits suitable for low voltage/low power operation. The proposed circuits have lower power supply voltage requirement, lower power dissipation and lower THD than the existing circuits available in literature. Both the circuits have been designed and simulated in Cadence virtuoso analog design environment using 180 nm CMOS technology. The simulation results have also been presented to validate the performance of the proposed circuits.

High-Precision Current Conveyor Based on BDQFG Miller Ota

The paper presents a sub-volt design of highly precise second-generation current conveyor (CCII  ) using Miller compensated Operational Transconductance Amplifier (OTA) designed using bulk driven quasi-floating gate (BDQFG) MOSFET. The bulk-driven approach help in working of proposed CCII  at low supply voltage. Moreover, followed BDQFG technique results in improves the transconductance and frequency response of the circuit over standalone bulk-driven technique. The proposed CCII  operates at  0.4V. Other performances which encourage its wide applicability are in terms of high current range and high bandwidth. The analysis of proposed current conveyor is carried in 0.18 m twin-well CMOS technology using HSpice.

Class AB amplifier with enhanced slew rate and GBW

SummaryThe design of a micropower class AB operational transconductance amplifier with large dynamic current to quiescent current ratio is addressed. It is based on a compact and power‐efficient adaptive biasing circuit and a class AB current follower using the quasi‐floating gate (QFG) technique. The amplifier has been designed and fabricated in a 0.5‐μm CMOS process. Simulation and measurement results show a slew rate (SR) improvement factor versus the class A version larger than 4 for the same supply voltage and bias currents, as well as enhanced small‐signal performance.

Super class AB-AB bulk-driven folded cascode OTA

A super class AB-AB bulk-driven folded cascode operational transconductance amplifier (OTA) with improved slew rate and unity-gain bandwidth is presented. The proposed bulk-driven amplifier utilizes the adaptively biased circuits, the bulk-driven flipped voltage follower and quasi-floating gate circuit, to implement the class-AB input stage and class-AB output stage respectively, which provides enhanced unity-gain bandwidth and dynamic current boosting. The proposed bulk-driven OTA is simulated on the 0.18 μm SMIC process with 1 V low voltage supply. The simulation results show that the proposed class AB-AB bulk-driven OTA achieves the increased factor of 6.5 and 4.7 in unity-gain bandwidth and slew rate compared with that of conventional class-A counterpart with only 50% extra power consumption.

Log Domain Integrator using Quasi-Floating Gate MOSFET

Background: A MOS transistor operating in weak inversion exhibits logarithmic behavior and could serve as replacement of bipolar transistors which have often been employed in implementing log domain circuits. However, threshold voltage restricts the operation of MOS based log domain circuits at low supply voltage which could be eliminated by floating gate transistors (FGMOS) at the cost of low gain, low output impedance and degraded bandwidth. These limitations can be further overcome by using quasi-floating gate MOSFET (QFGMOS).The log domain technique has been employed to enhance the dynamic range of analog circuits suitable of operation at low supply voltage. Methods: In this paper, we have designed QFGMOS based integrator and its performance has been compared with CMOS and FGMOS versions. The behavior of these circuits has been verified by using OrCAD PSpice with level 7 parameters for 0.13 µm technology obtained from TSMC with supply voltage of 1V. Results: It has been observed that QFGMOS based compressor and expander exhibits better performance as compared to their CMOS and FGMOS counterparts. Further QFGMOS based log domain integrator has been designed and its performance compared with that of CMOS and FGMOS based log domain integrators and found that QFGMOS based log domain integrator exhibits larger bandwidth (4.26 MHz) as compared to FGMOS (3.2 MHz) and it dissipates less power (88.7 µW) then FGMOS (0.114 mW) and CMOS (0.129 mW) based log domain integrators and could be useful for low voltage applications. Conclusion: In this paper functional blocks of log domain integrator like compressor and expander have been designed using CMOS, FGMOS, QFGMOS transistors and their performance studied through PSpice simulations. It has been observed that QFGMOS based compressor and expander exhibits better performance as compared to their CMOS and FGMOS counterparts. Further QFGMOS based log domain integrator has been designed and its performance compared with that of CMOS and FGMOS based log domain integrators. Keywords: Compressor, expander, integrator, log domain, weak inversion, threshold voltage.

A Class-AB Bulk-Driven Amplifier with Enhanced Transconductance Using Quasi-Floating Gate Method

This paper presents a supper class-AB adaptive biasing bulk-driven amplifier for ultra-low-power applications. In the proposed structure, two bulk-driven flipped voltage follower (FVF) cells are reconfigured as nonlinear tail currents using quasi-floating gate method to enhance transconductance and slew rate. In addition, two idle current controllers are employed as common source amplifiers to provide a supper class-AB structure without increasing total current consumption. The proposed structure is simulated in 0.18-[Formula: see text]m CMOS technology at 0.5[Formula: see text]V supply with 35[Formula: see text]nW power budget. The results show a 57.9[Formula: see text]dB DC gain, 8.8[Formula: see text]kHz gain bandwidth and 38.2[Formula: see text]V/ms slew rate for the proposed amplifier.

A CMOS Low-Voltage Super Follower Using Quasi-Floating Gate Techniques

A quasi-floating gate (QFG) “super-follower” is presented. The high resistance used by the QFG transistor is constructed by two diodes connected back-to-back, leading to a simple-, temperature-stable- and small-area solution. Expressions for the behavior of the follower are introduced and verified by circuit simulations in LTSPICE using 0.5[Formula: see text][Formula: see text]m CMOS process models, which show an improved performance of the proposed circuit with respect to the original super-follower. To prove the principle, a test cell was fabricated in the same 0.5[Formula: see text][Formula: see text]m CMOS technology and characterized. Measurement results show a gain-bandwidth product of 10[Formula: see text]MHz and power consumption of 120[Formula: see text][Formula: see text]W with a 1.5[Formula: see text]V single supply.

Reliable Low Voltage Circuit Design Techniques

In this paper, non-conventional circuit design techniques has been reviewed. The techniques discussed are widely used for realizing low voltage low power analog circuits. The discussed techniques in this paper are: Bulk Driven, Floating and Quasi-floating Gate followed by operating of Bulk Driven MOSFET in Floating and Quasi-floating Gate mode. In all the approach, the threshold voltage restriction is removed or reduced from the input signal path thereby reducing the power consumption. However, the adverse effect lies is terms of reduced performance parameters of MOSFET compared to conventional gate driven MOSFET parameters as shown in this paper through simulation results. The comparative analysis of MOSFET parameters results in encouragement of two approaches: Quasi-floating Gate and Bulk Driven Quasi-floating Gate MOSFET. Each of these approaches has its advantage in specific domains. Further in this paper, an Operational Transconductance Amplifier is proposed which use the Bulk Driven Quasi-floating Gate MOSFET technique and the same is amplifier under similar conditions is also realized using Bulk Driven MOSFET so as to highlight the advantage of Bulk Driven Quasi-floating Gate MOSFET over Bulk Driven MOSFET. All the performances metrics are achieved with the help of HSpice simulator using MOSFET models of 180nm technology provided by UMC.

Low‐voltage fully differential difference transconductance amplifier

A new complementary metal-oxide-semiconductor (CMOS) structure for fully differential difference transconductance amplifier (FDDTA) is presented in this study. Thanks to using the non-conventional quasi-floating-gate (QFG) technique the circuit is capable to work under low-voltage supply of 0.6 V with extended input voltage range and with class AB output stages. The QFG multiple-input metal-oxide-semiconductor transistor is used to reduce the count of the differential pairs that needed to realise the FDDTA with simple CMOS structure. The static power consumption of the proposed FDDTA is 40 μW. The FDDTA was designed in Cadence platform using 0.18 μm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC). As an example of applications a three-stage quadrature oscillator and fifth-order elliptic low-pass filter are presented to confirm the attractive features of the proposed CMOS structure of the FDDTA.

Design and Analysis of an Ultra-Low-Power Second-Order Asynchronous Delta–Sigma Modulator

In this paper, a second-order asynchronous delta–sigma modulator is proposed based on the active-RC integrators. The operational transconductance amplifiers used in the integrators are improved by employing a class-AB structure with bulk-driven input drivers and quasi-floating gate method in subthreshold region. These circuitry approaches provide better linearity, signal-to-noise ratio and speed for the integrators and hence an overall improvement in the performance of the modulator. Mathematical analyses of the second-order modulator confirm a higher center frequency compared to a first-order one. The increased center frequency transfers redundancy distortions to higher frequencies, which results in wider input bandwidth and better linearity. The proposed ASDM designed in TSMC 130 nm CMOS Technology with a center frequency of 1.73 kHz at supply voltage of 250 mV with a signal-to-noise-plus-distortion ratio of 67.3 dB and the power consumption of 30 nW.

High gain amplifier with feedforward compensation based on quasi-floating gate transistors

In this paper, a two-stage amplifier with feedforward frequency compensation scheme is presented. Because the frequency compensation scheme uses the amplifier's second stage gm to create the feedforward path no additional circuitry is needed. To verify the proposed scheme a prototype was fabricated using 0.5μm technology. Measurements results demonstrate a high DC gain, 18MHz of gain-bandwidth product and 86° phase margin are achieved with an output load capacitance of 80pF.

A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique

This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.

A Novel Design of Low-Voltage VDIBA and Filter Application

In this study, a low-voltage low-power design of previously introduced analog signal processing element called as Voltage Differencing Inverting Buffered Amplifier (VDIBA) is presented. Level shifter current mirrors are used in the circuit design in order to accomplish the low-voltage low-power operation. The configuration operates only with ±0.4 V supply voltages and consumes power 569 µW at the bias current 50 µA. Also, low-voltage transconductor which has highly linear g m is executed with the use of bulk-driven quasi-floating gate (BD-QFG) and source degeneration techniques. The simulations of the introduced circuit have been performed with 0.18 μm TSMC CMOS technology by SPICE. The theoretical approaches have been confirmed by the simulation results. DOI: http://dx.doi.org/10.5755/j01.eie.22.6.17224

Simulation and Performance Analysis of Low Power Quasi Floating Gate PCS Model

The Spice Model for photo catalytic sensor (PCS) proposed by Whig and Ahmad overcome several drawbacks like complex designing, non-linearity and long computation time generally found in Flow Injection Analysis (FIA) technique by Yoon-Chang Kim et al for the determination of Chemical Oxygen Demand (COD). FIA technique involves the complete analysis including sampling and washing. Flow Injection Analysis is analytical method for the measurement of chemical oxygen demand using photochemical column. This method uses a bulky setup and takes 10-15 minutes to get the output result which is a tedious and time consuming job. If conventional method is continuously used for a long time than it is stable only for 15 days. The purpose of this paper is to propose a new Quasi Floating Gate Photo Catalytic Sensor (QFGPCS) approach which has low power consumption and compared the results with the conventional models. The proposed model operates under sub threshold conditions which are appreciated in large integrated system design. The results of simulation were found to be fairly in agreement with the theoretical predictions. The results are exhibited near linear variations of parameters of interest with appreciably reduced response time.

Low-Power Analog Channel Selection Filtering Techniques

Various techniques to reduce power consumption in the channel selection filtering of wireless receivers are discussed. They include class AB operation by the use of quasi-floating gate transistors and reuse of circuital blocks. A mixed continuous/discrete frequency tuning approach set by a simple on-chip automatic tuning circuit is also presented, which allows wide tuning range with modest area and power requirements. The techniques presented are illustrated by a third-order CMOS Gm-C channel filter designed for a dual-mode Bluetooth/ZigBee zero-IF receiver, with two different on-chip automatic tuning circuits. Measurement results for a test chip prototype in a 0.5- $${\upmu }$$μm CMOS process are presented, showing in-band filter IIP3 >20 dBVp with a power consumption of 3.65 mW for both Bluetooth and ZigBee modes, and the required frequency tuning range set by the automatic tuning circuits.

Designing a XOR Gate Circuit based on Floating Gate and Quasi-Floating Gate

Designing a XOR Gate Circuit based on Floating Gate and Quasi-Floating Gate

Low voltage high performance bulk driven quasi-floating gate based self-biased cascode current mirror

A low voltage high performance self-biased cascode current mirror in terms of output resistance and bandwidth is proposed in this paper. The proposed current mirror enhances the output resistance in range of mega ohms and also shows a significant improvement in bandwidth compared to prior arts. The current mirror is designed using bulk-driven technique which helps it to operate at very low supply voltage of ±0.2V. To achieve high output resistance, the proposed current mirror uses the super cascode stage at its output. Furthermore, an external capacitor is used which accounts for increasing the bandwidth. Small-signal analysis carried proves the improvement achieved by proposed architecture. The current mirror operates well for wide input current range from 0 to 200μA with good linearity and shows the bandwidth of 415MHz. The observed input and output resistance is 300Ω and 212MΩ respectively. Further, the THD and mismatch analysis is carried to prove the robustness of proposed current mirror. The complete analysis of proposed current mirror is shown using HSpice simulations on UMC 0.18μm technology.

A High Performance Bulk Driven Quasi Floating Gate MOSEFT Based Current Mirror

A high performance low voltage bulk driven quasi floating gate MOS based current mirror has been proposed. The combination of bulk driven and quasi FGMOS decreases the input impedance upto 120Ω which is four times smaller than current mirror based on only bulk driven technique. The bandwidth has also been improved upto 173MHz which is three folds of bandwidth of conventional bulk driven current mirror. Very high output impedance upto 1GΩ is achieved using self cascode technique in output section depending the value of factor m. Small signal analysis of proposed circuit verifies the simulated results. The circuit is simulated using 0.18μm CMOS technology with supply voltage of ±0.3V. The proposed current mirror is highly suitable for low voltage applications.