Abstract
This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.
Highlights
Voltage followers or buffers are basic analog building blocks widely used as output stage in integrated circuits to drive low-level signals into loads owning large capacity
During the past fifteen years, different circuit approaches have been proposed, such techniques range from the use of multipleinput floating-gate transistors (Ramirez-Angulo, 1995), Quasi-Floating-Gate (QFG) transistors (Ramirez-Angulo, 2003), and recently bulk-driven techniques (Haga, 2009). This last approach has become popular because it bases its low-power supply performance-capability in the reduction of the threshold voltage of P-MOS transistors by means of the body effect (Tsividis, 2010)
Transistors M1 to M3 form the basic structure of the flipped voltage follower (FVF) circuit, while M6 and high resistance device (HiR) construct the biasing point for M5, which is the QFG device
Summary
Voltage followers or buffers are basic analog building blocks widely used as output stage in integrated circuits to drive low-level signals into loads owning large capacity. Transistors M1 to M3 form the basic structure of the FVF circuit, while M6 and HiR construct the biasing point for M5, which is the QFG device This transistor achieves class AB operation for this circuit in combination with M1; the circuit can be explained as follows: Considering large signal operation, the voltage swing at node “x” is coupled to gate of M5 through C1; if Vx rises, M5 is turned-off while vgsM1 is increased allowing M1 to sink large amounts of current from the output load. The output of this filter is connected to node “x”, isolating biasing and signal of M5, being this cut-off frequency the minimum value for which the QFG technique has real effect over the circuit (Lopez-Martin, 2011).
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