Design and Analysis of an Ultra-Low-Power Second-Order Asynchronous Delta–Sigma Modulator

Abstract

In this paper, a second-order asynchronous delta–sigma modulator is proposed based on the active-RC integrators. The operational transconductance amplifiers used in the integrators are improved by employing a class-AB structure with bulk-driven input drivers and quasi-floating gate method in subthreshold region. These circuitry approaches provide better linearity, signal-to-noise ratio and speed for the integrators and hence an overall improvement in the performance of the modulator. Mathematical analyses of the second-order modulator confirm a higher center frequency compared to a first-order one. The increased center frequency transfers redundancy distortions to higher frequencies, which results in wider input bandwidth and better linearity. The proposed ASDM designed in TSMC 130 nm CMOS Technology with a center frequency of 1.73 kHz at supply voltage of 250 mV with a signal-to-noise-plus-distortion ratio of 67.3 dB and the power consumption of 30 nW.