Quasi-cyclic Low-density Parity-check Research Articles

Reconstruction-Computation-Quantization (RCQ): A Paradigm for Low Bit Width LDPC Decoding

This paper uses the reconstruction-computation-quantization (RCQ)paradigm to decode low-density parity-check (LDPC) codes. RCQ facilitates dynamic non-uniform quantization to achieve good frame error rate (FER) performance with very low message precision. For message-passing according to a flooding schedule, the RCQ parameters are designed by discrete density evolution. Simulation results on an IEEE 802.11 LDPC code show that for 4-bit messages, a flooding Min Sum RCQ decoder outperforms table-lookup approaches such as information bottleneck (IB) or Min-IB decoding, with significantly fewer parameters to be stored. Additionally, this paper introduces layer-specific RCQ, an extension of RCQ decoding for layered architectures. Layer-specific RCQ uses layer-specific message representations to achieve the best possible FER performance. For layer-specific RCQ, this paper proposes using layered discrete density evolution featuring hierarchical dynamic quantization (HDQ) to design parameters efficiently. Finally, this paper studies field-programmable gate array (FPGA) implementations of RCQ decoders. Simulation results for a (9472, 8192) quasi-cyclic (QC) LDPC code show that a layered Min Sum RCQ decoder with 3-bit messages achieves more than a 10% reduction in LUTs and routed nets and more than a 6% decrease in register usage while maintaining comparable decoding performance, compared to a 5-bit offset Min Sum decoder.

Joint Semi-Blind Self-Interference Cancellation and Equalisation Processes in 5G QC-LDPC-Encoded Short-Packet Full-Duplex Transmissions.

The paper proposes a joint semi-blind algorithm for simultaneously cancelling the self-interference component and estimating the propagation channel in 5G Quasi-Cyclic Low-Density Parity-Check (QC-LDPC)-encoded short-packet Full-Duplex (FD) transmissions. To avoid the effect of channel estimation processes when using short-packet transmissions, this semi-blind algorithm was developed by taking into account only a small number (four at least) pilot symbols, which was integrated with the intended information sequence and used for the feedback loop of the estimation of the channels. The results showed that this semi-blind algorithm not only achieved nearly optimal performance, but also significantly reduced the processing time and computational complexity. This semi-blind algorithm can also improve the performances of the Mean-Squared Error (MSE) and Bit Error Rate (BER). The results of this study highlight the potential efficiency of this joint semi-blind iterative algorithm for 5G and Beyond and/or practical IoT transmission scenarios.

Real-Time FPGA Investigation of Interplay Between Probabilistic Shaping and Forward Error Correction

In this work, we implement a complete probabilistic amplitude shaping (PAS) architecture on a field-programmable gate array (FPGA) platform to study the interplay between probabilistic shaping (PS) and forward error correction (FEC). Due to the fully parallelized input–output interfaces based on look up table (LUT) and low computational complexity without high-precision multiplication, hierarchical distribution matching (HiDM) is chosen as the solution for real time probabilistic shaping. In terms of FEC, we select two kinds of the mainstream soft decision-forward error correction (SD-FEC) algorithms currently used in optical communication system, namely Open FEC (OFEC) and soft-decision quasi-cyclic low-density parity-check (SD-QC-LDPC) codes. Through FPGA experimental investigation, we studied the impact of probabilistic shaping on OFEC and LDPC, respectively, based on PS-16QAM under moderate shaping, and also the impact of probabilistic shaping on LDPC code based on PS-64QAM under weak/strong shaping. The FPGA experimental results show that if pre-FEC bit error rate (BER) is used as the predictor, moderate shaping induces no degradation on the OFEC performance, while strong shaping slightly degrades the error correction performance of LDPC. Nevertheless, there is no error floor when the output BER is around 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-15</sup> . However, if normalized generalized mutual information (NGMI) is selected as the predictor, the performance degradation of LDPC will become insignificant, which means pre-FEC BER may not a good predictor for LDPC in probabilistic shaping scenario. We also studied the impact of residual errors after FEC decoding on HiDM. The FPGA experimental results show that the increased BER after HiDM decoding is within 10 times compared to post-FEC BER.

Area- and Energy-Efficient LDPC Decoder Using Mixed-Resolution Check-Node Processing

A practical min-sum algorithm is associated with tree-based comparison units for the check-node operation, being a major bottleneck in designing low-cost and energy-efficient low-density parity-check (LDPC) decoders. In this brief, we present a cost-effective LDPC decoder architecture by changing its internal computing resolution for the power-hungry check-node processing. The proposed mixed-resolution comparison offers significant advantages in terms of both area and energy, while achieving error-correcting performance within 0.3 dB of the previous normalized min-sum (NMS) algorithm for a (1644, 1408) quasi-cyclic LDPC code of the 5G New Radio specifications. Compared to the baseline NMS architecture, the proposed decoder in a 65-nm CMOS technology reduces the hardware complexity and the power consumption by 28.4% and 23.1%, respectively, enhancing the area efficiency by more than 88.2%.

Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders.

This paper presents a low-complexity multi-size circular-shift network (MCSN) structure for 5th-generation (5G) New Radio (NR) quasi-cyclic low-density parity-check (QC-LDPC) decoders. In particular, a fine-coarse approach-based multi-size cyclic shift network, which decomposes the cyclic shift size into fine part and coarse part, is introduced. The proposed MCSN structure is composed of a pre-rotator performing the fine part of the cyclic shift, and a main rotator executing the coarse part of the cyclic shift. In addition, a forward routing circular-shift (FRCS) network, which is based on the barrel shifter and the forward routing process is presented. The proposed switch network is able to support all 51 different submatrix sizes as defined in the 5G NR standard through an efficient forward routing switch network and help reduce the hardware complexity using a cyclic shift size decomposition method. The proposed MCSN is analyzed, and indicates a substantial reduction in the hardware complexity. The experimental results on TSMC 65-nm CMOS technology show that the proposed MCSN structure for 5G NR LDPC decoder offers an area saving up to 56.75% compared to related works in the literature.

Joint Iterative Blind Self-Interference Cancellation, Propagation Channel Estimation and Decoding Processes in Full-Duplex Transmissions

The paper proposes a joint blind iterative Self-Interference (SI) cancellation, propagation channel estimation and decoding algorithm in Full-Duplex (FD) transmissions via feedback of channel estimates and decoded messages combined with the process of Digital Self-Interference Cancellation (DSIC). Different from the conventional algorithm, the proposed blind algorithm simultaneously estimates the self-interference and propagation channels and decodes messages in each decoding iteration of 5G Quasi-Cyclic Low Density Parity Check (QC-LDPC) codes. The temporary propagation channel estimate and decoded message are fed back to improve the self-interference cancellation and also the channel estimation as well as decoding in the next iteration. The results show that the proposed algorithm outperforms the conventional algorithm, especially at high signal to noise ratio (SNR) and small number of symbols, and requires much less processing time and computational complexity while achieving the convergence performance. The results also show that the proposed algorithm is less sensitive to SI level than the conventional algorithm. The paper further proposes a partial feedback scheme, which only use few feedback symbols for channel estimation, to significantly reduce the processing time and computational complexity while maintaining the performance. These good properties seem quite suitable for a use of this proposed blind iterative algorithm for short-length packet FD transmissions in Internet-of-Things (IoT) applications and green communications.

Integer Ring Sieve for Constructing Compact QC-LDPC Codes With Girths 8, 10, and 12

This paper proposes a new method of constructing compact fully-connected Quasi-Cyclic Low Density Parity Check (QC-LDPC) codes with girth <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g$ </tex-math></inline-formula> = 8, 10, and 12. The originality of the proposed method is to impose constraints on the exponent matrix P to reduce the search space drastically. For a targeted lifting degree of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> , the first step of the method is to sieve the integer ring <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbb {Z}_{N}$ </tex-math></inline-formula> to make a particular sub-group with specific properties to construct the second column of P (the first column being filled with zeros). The remaining columns of P are determined recursively as multiples of the second column by adapting the sequentially multiplied column (SMC) method whereby a controlled greedy search is applied at each step. The codes constructed with the proposed semi-algebraic method show lengths that can be significantly shorter than their best counterparts in the literature.

(7,K) GIRTH-8 QC-LDPC CODES WITH AN EXPLICIT CONSTRUCTION

Recently, for each row weight $K$ and column-weight $J$, $3le J< K$, several classes of $(J,K)$ quasi-cyclic (QC) low-density parity-check (LDPC) codes with girth 8 have been constructed explicitly such that their corresponding lower-bounds on the size of circulant permutation matrices (CPMs) have been considered small as possible. In this paper, for $J=7$, a class of $(7,K)$ QC-LDPC codes with girth 8 is generated by an explicit method such that the lower-bounds of the constructed codes remarkably are better than the state-of-the-art bound $(K-1)(K^2+K)+1$.

Recovering the Parameters of an LDPC Code From Noisy Intercepted Sequences

Blind identification of channel codes is a key technology in non-cooperative communication as well as intelligent communication. In this letter, we are interested in recovering the parameters of low-density parity-check (LDPC) codes without any a priori information. We propose to find dual codewords from noisy intercepted sequences and prove that the problem is NP-complete. Afterward, we propose an improved collision-based algorithm that can avoid most of the invalid searches and thus allowing a significant reduction in complexity. The algorithm produces almost no errors when the noise is small. While in the case of non-negligible noise, we propose to use soft information to detect the outputs of the algorithm, and errors in which can therefore be extensively eliminated. After a sufficient number of dual codewords have been found, one can easily recover the code lengths and code rates of LDPC codes, as well as the sizes of sub-matrices for Quasi-Cyclic LDPC codes. Experimental results show that the proposed method has an improved noise tolerance and can be more efficient than existing methods.

Quantum LDPC Codes With Almost Linear Minimum Distance

We give a construction of quantum LDPC codes of dimension $\Theta(\log N)$ and distance $\Theta(N/\log N)$ as the code length $N\to\infty$. Using a product of chain complexes this construction also provides a family of quantum LDPC codes of distance $\Omega(N^{1-\alpha/2}/\log N)$ and dimension $\Omega(N^\alpha \log N)$, where $0 \le \alpha < 1$. We also introduce and study a new operation called lifted product, which naturally generalizes the product operations for quantum codes and chain complexes. Moreover, as a simple byproduct of our results on quantum codes, we obtain a new result on classical codes. We show that for any fixed $R < 1$ there exists an asymptotically good family of classical quasi-cyclic LDPC codes of rate at least $R$ with, in some sense, optimal circulant size $\Omega(N/\log N)$ as the code length $N\to\infty$.

Some New Constructions of Girth-8 QC-LDPC Codes for Future GNSS

In this letter, we propose a new construction of girth-8 Quasi-Cyclic Low-Density Parity-Check codes (QC-LDPC) with various lengths for the global navigation satellite systems (GNSS). This scheme combines two steps. The first is the construction of a family of regular girth-8 QC-LDPC codes of various lengths and rates with two designed sequences. The second is the performance improvement of those from the first construction of half-rate cases using a proposed weight matrix so that the result becomes type-II QC-LDPC codes. This results in some final codes with short lengths of 600, 1200, and 1800, especially for future GNSS. We performed a simulation and confirmed that the proposed QC-LDPC codes of lengths 600 and 1200 have an additional coding gain about 0.3 dB at frame error rate 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−5</sup> over the LDPC codes used in the Global Positioning System.

Construction of Multi-Rate Quasi-Cyclic LDPC Codes for Satellite Communications

To provide reliable transmissions with flexible rates for satellite communications, this paper presents a novel method of constructing multi-rate quasi-cyclic low-density parity-check (LDPC) codes. The basic idea is to generate low-rate codes from a high-rate mother code by combining shortening and extending, which ensures that the generated code family owns the same code length, in order to maintain the same frame structure. The code construction involves the design of base matrices and exponent matrices for the designed codes. A progressive row elimination and addition algorithm is proposed for designing the code base matrices from a high rate to low rates. This algorithm leads to the nested and systematic structure of the parity-check matrices, which are desirable for practical implementations of their encoders and decoders, while ensuring the optimal decoding thresholds. In addition, we construct a circulation coefficient matrix based on finite fields and select the optimal rows in this matrix to construct exponent matrices while considering of cycle structures. We demonstrate that the designed codes achieve better performance for all the code rates than the LDPC codes in DVB-S2X standards. In addition, the proposed codes do not exhibit error floors for their block error rates down to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−5</sup> .

Reliability-aware subcarrier mapping strategy of QC-LDPC encoded symbols in bandwidth-limited IM/DD OFDM systems.

We propose a simple yet effective strategy to map forward error correction (FEC) encoded symbols to subcarriers in bandwidth-limited intensity-modulation and direct-detection (IM/DD) optical orthogonal frequency division multiplexing (OFDM) systems. The design exploits the reliability diversity of OFDM subcarriers in bandwidth-limited systems and allocates FEC encoded systematic symbols and parity-check symbols to high-reliability and low-reliability subcarriers, respectively. In contrast to adaptively-loaded OFDM or systems using multiple sets of FECs with different code rates for different subcarriers, the proposed design does not induce additional complexity and avoids the round-trip delay between transceivers. We investigate the performance of the proposed design in quasi-cyclic low-density parity-check (QC-LDPC) coded OFDM system under different decoding iterations. Experimental results of 120-Gb/s signals over 2 km and 100-Gb/s signals over 5 km show that the OFDM system using the proposed mapping strategy is superior to both OFDM and discrete-Fourier-transform spread (DFT-S) OFDM using conventional mappings without considering the subcarrier diversity or using pre-equalization, regardless of the received optical power, the FEC code rate, the length of the cyclic prefix, the transmission distance, the number of decoding iterations, and the degree distribution of the QC-LDPC optimized under either an infinite or a limited number of iterations. The proposed mapping is optimal when the systematic symbols and parity-check symbols are exactly loaded to high-reliability and low-reliability subcarriers respectively. The studies enable the proposed strategy promising for bandwidth-limited IM/DD OFDM systems such as low-latency data center interconnects.

Reduced-complexity decoding implementation of QC-LDPC codes with modified shuffling

Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm for decoding low-density parity-check (LDPC) codes. Such a schedule for LDPC codes has, in general, reduced implementation complexity compared to a fully parallel architecture and higher convergence rate compared to both serial and parallel architectures, regardless of the codeword length or code-rate. In this paper, we introduce a modified shuffling method which shuffles the rows of the parity-check matrix (PCM) of a quasi-cyclic LDPC (QC-LDPC) code, yielding a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. The proposed shuffling scheme additionally guarantees the columns of a layer of the shuffled PCM to be either zero weight or single weight. This condition has a key role in further decreasing LD complexity. We show that due to these two properties, the number of occupied look-up tables (LUTs) on a field programmable gate array (FPGA) reduces by about 93% and consumed on-chip power by nearly 80%, while the bit error rate (BER) performance is maintained. The only drawback of the shuffling is the degradation of decoding throughput, which is negligible for low values of E_b/N_0 until the BER of 1e−6.

Low-Latency QC-LDPC Encoder Design for 5G NR.

In order to meet the low latency and high throughput requirements of data transmission in 5th generation (5G) New Radio (NR), it is necessary to minimize the low power encoding hardware latency on transmitter and achieve lower base station power consumption within a fixed transmission time interval (TTI). This paper investigates parallel design and implementation of 5G quasi-cyclic low-density parity-check (QC-LDPC) codes encoder. The designed QC-LDPC encoder employs a multi-channel parallel structure to obtain multiple parity check bits and thus reduce encoding latency significantly. The proposed encoder maps high parallelism encoding algorithms to a configurable circuit architecture, achieving flexibility and support for all 5G NR code length and code rate. The experimental results show that under the 800 MHz system frequency, the achieved data throughput ranges from 62 to 257.9 Gbps, and the maximum code length encoding time under base graph 1 (BG1) is only 33.75 ns, which is the critical encoding time of our proposed encoder. Finally, our proposed encoder was synthesized on SMIC 28 nm CMOS technology; the result confirmed the effectiveness and feasibility of our design.

Relation Between GCD Constraint and Full-Length Row-Multiplier QC-LDPC Codes With Girth Eight

The greatest-common-divisor (GCD) method is a general framework employing a set of simple inequalities (called GCD constraint) to guarantee girth eight for a class of (J,L) quasi-cyclic (QC) low-density parity-check (LDPC) codes. However, an important problem, i.e., whether the GCD constraint is necessary for this class of codes to have girth eight, remains open. In this letter, the question is answered affirmatively, following which a novel algorithm aiming to find the shortest codes with girth eight in such a class is proposed. Besides, a close connection is established between the GCD method and the base expansion method, which are both applicable for any J and any L.

Error Floor Analysis of LDPC Row Layered Decoders

In this paper, we analyze the error floor of quasi-cyclic (QC) low-density parity-check (LDPC) codes decoded by the sum-product algorithm (SPA) with row layered message-passing scheduling. For this, we develop a linear state-space model of trapping sets (TSs) which incorporates the layered nature of scheduling. We demonstrate that the contribution of each TS to the error floor is not only a function of the topology of the TS, but also depends on the row layers in which different check nodes of the TS are located. This information, referred to as TS layer profile (TSLP), plays an important role in the harmfulness of a TS. As a result, the harmfulness of a TS in particular, and the error floor of the code in general, can significantly change by changing the order in which the information of different layers, corresponding to different row blocks of the parity-check matrix, is updated. We also study the problem of finding a layer ordering that minimizes the error floor, and obtain row layered decoders with error floor significantly lower than that of their flooding counterparts. As part of our analysis, we make connections between the parameters of the state-space model for a row layered schedule and those of the flooding schedule. Simulation results are presented to show the accuracy of analytical error floor estimates.

Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA

The quasi-cyclic (QC) low-density parity-check (LDPC) code is a key error correction code for the fifth generation (5G) of cellular network technology. Designed to support several frame sizes and code rates, the 5G LDPC code structure allows high parallelism to deliver the high demanding data rate of 10 Gb/s. This impressive performance introduces challenging constraints on the hardware design. Particularly, allowing such high flexibility can introduce processing rate penalties on some configurations. In this context, a novel highly parallel and flexible hardware architecture for the 5G LDPC decoder is proposed, targeting field-programmable gate array (FPGA) devices. The architecture supports frame parallelism to maximize the utilization of the processing units, significantly improving the processing rate. The controller unit was carefully designed to support all 5G configurations and to avoid update conflicts. Furthermore, an efficient data scheduling is proposed to increase the processing rate. Compared to the recent related state of the art, the proposed FPGA prototype achieves a higher processing rate per hardware resource for most configurations.

Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency

Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE.

High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.