Abstract
Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE.
Highlights
Fifth-generation wireless technology standard for broadband cellular networks (5GNR) [1] introduces low-density parity-check (LDPC) codes [2] for data channel coding
In cases when the LDPC code is systematic, the parity check matrices (PCM) can be partitioned into two submatrices (H = H1 H2 ), where the first submatrix is of size m × k, and the second submatrix is of size m × m
PCM has a structure designed to support decoder efficiency, it can be processed in a way that is optimal for the encoder
Summary
Fifth-generation wireless technology standard for broadband cellular networks (5G. NR) [1] introduces LDPC codes [2] for data channel coding. 5G NR LDPC codes are highly irregular and their base graph matrices are mostly sparse This property drastically reduces the efficiency of highly parallel architectures since many hardware processing units frequently remain idle. The main contributions of this paper are (1) high flexibility of the LDPC encoder that supports all codes from 5G NR This is primarily obtained by the proper design of a circular shifting network, which is the key hardware processing unit in the system; (2) by exploiting partially parallel processing, the circular shifter and other hardware processing units are rarely idle, which highly increases the hardware usage efficiency; and (3) the encoder is capable of changing the encoding schedule in runtime so as to exploit high parallelism both for codes with high values of lifting size and for codes with smaller lifting sizes.
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