Quantum-dot Cellular Automata Circuits Research Articles

Simple, robust and systematic QCA clocking scheme for area-efficient nanocircuits

ABSTRACT Quantum-dot cellular automata (QCA) represent an innovative forefront in nanotechnology, exploring the utilisation of quantum dots as carriers of data in computational systems. Temporal controls govern the coordination of information transmission and synchronisation within QCA circuits. Nevertheless, most research in QCA overlooks the crucial aspect of appropriately arranging the fundamental clocking mechanism. Consequently, QCA circuits often exhibit irregularities in their clocking regions, rendering them unsuitable for practical implementation. Adopting a consistent and scalable clocking framework is necessary to address this challenge and facilitate efficient design with optimal routing possibilities within clocking zones. Without a clearly defined and standardised clocking structure, QCA circuit designs remain incomplete and lack viability for fabrication. Numerous QCA clocking methodologies have been proposed, showcasing commendable ingenuity. Nonetheless, these approaches exhibit room for enhancement, particularly in tackling issues concerning design intricacies, such as establishing robust feedback loops and efficient area utilisation. A novel approach termed Simple, Robust and Systematic (SRS) scheme has been introduced in response to these challenges. Emphasising heightened feedback pathways, optimal spatial allocation and streamlined design, this scheme aims to overcome existing limitations.

Analysis of fault tolerance capability of QCA circuit under regular clocking

ABSTRACT With significant progress in device scaling, current CMOS technology faces challenges such as low device density and increased power dissipation. Quantum-dot Cellular Automata (QCA) stands as one of the alternative nanotechnologies that proved viable to overcome these hurdles. The fundamental building block for implementing logic circuits is a QCA cell, which includes two vertically positioned electrons within four quantum dots. The majority gate and inverters are considered to be the fundamental primitives in QCA. On the other hand, clocking serves a crucial part in ensuring the correct synchronisation and information transmission within a circuit. Furthermore, regular clocking resolves fabrication pitfalls at the nanoscale and supports scalability. However, defects remain a concern in nanoscale circuit realisation. This research investigates the performance of logic circuits realised in regular clocking concerning the potentiality to tolerate faults. The circuits in both combinational and sequential logic are examined. For this purpose, the HDLQ and QCADesigner simulators are utilised. In accordance with the investigation, the performance of the circuits realised using zig–zag clocking is noteworthy, whereas the USE clock is noticed in a few cases.

Efficient adders for nano computing: an approach using QCA

Abstract This research paper presents a detailed evaluation of Quantum-dot Cellular Automata (QCA) digital adder designs utilizing advanced analytical tools, specifically QCADesigner, QCAPro, and QCADesigner-E. The study introduces novel adder designs that significantly enhance cell efficiency, reduce latency, and optimize cost. The study underscores the benefits of using coplanar crossovers to reduce fabrication complexity and avoid additional cell layers, which helps maintain high polarization levels and operational efficiency. The proposed full adder, built using a three-input XOR gate, shows a significant 88% reduction in QCA-specific cost (QSC) and a 0.5 clock cycle reduction in latency compared to the best-optimized existing designs. This improvement is achieved by integrating a single majority gate and MMV gate, removing the need for inverters and consuming 144.2 meV of energy. This design offers a major enhancement over previous designs, which lack such thorough evaluations. Additionally, the proposed ripple carry adder uses 40 fewer cells, achieves a 0.75 clock cycle reduction in latency over the best available design, provides an 81% improvement in QSC, and demonstrates a fully scalable and reliable circuit suitable for nanocomputing applications. Furthermore, the study introduces a single-bit carry look-ahead adder based on half-adder instantiation, with the proposed four-bit carry look-ahead adder achieving a 14% improvement in QCA-specific cost, highlighting its innovative features and practical advantages for advanced QCA circuits.

Circuits for the spectroscopic readout of bits from molecular quantum-dot cellular automata

Molecular quantum-dot cellular automata (QCA) may provide high speed, low-power, classical information processing in the post-CMOS era. The readout of molecular QCA bits is challenging because the molecules may be much smaller than transistors and even single-electron transistors. This paper builds on a recent proposal for the spectroscopic readout of bits from asymmetric QCA molecules. Here, we propose circuits for fanning out a bit onto a large QCA circuit to increase the spectroscopic signal-to-noise ratio. As the number of molecules in a fanout circuit grows, the internal bias of each asymmetric cell accumulates, and the circuit may become stuck, tolerating only a very small internal bias. We also propose the use of an applied electric field to compensate for a candidate molecule’s internal bias, thereby restoring switchability, even when the internal bias is significant.

Test generation algorithm for QCA circuits targeting novel defects and its corresponding fault models

Considering the scaling limitations of current Complementary Metal Oxide Semiconductor (CMOS) technology, Quantum-dot-Cellular Automata (QCA) is emerging as one of the alternatives. QCA being at the molecular scale, defects are more likely to occur in it. Therefore, substantial development of QCA-oriented defects, its corresponding fault models and test generation is required. In this paper, a test generation algorithm for a QCA combinational circuit is proposed. The FAN (A Fanout Oriented) test generation algorithm is extended for QCA. The proposed Automatic Test Pattern Generator (ATPG) for QCA targets Single Stuck at Fault (SSF) set produced by novel Multiple Missing Cells (MMC) defects. The proposed ATPG is based on the QCA-oriented test generation properties and guided by proposed testability measures.The MCNC benchmark circuits are synthesized into QCA using proposed synthesis algorithms to check the effectiveness of the proposed ATPG. The ATPG is developed using C++ and tested on MCNC benchmark circuits. Further, ATPG-generated test vectors are validated at the QCA device level to demonstrate their correctness. The QCADesigner-E tool is used for the device-level implementation of the MCNC benchmark circuit.

Design and analysis of a fault tolerance nano-scale code converter based on quantum-dots

Quantum-dot cellular automata (QCA), a nano-scale computer framework, is developing as a potential alternative to current transistor-based technologies. However, it is susceptible to a variety of fabrication-related errors and process variances because it is a novel technology. As a result, QCA-based circuits pose reliability-related problems since they are prone to faults. To address the dependability challenges, it is becoming increasingly necessary to create fault-tolerance QCA-based circuits. On the other hand, the applications of code converters in digital systems are essential for rapid signal processing. Using fault-tolerance XOR and multiplexer, this research suggests a nano-based binary-to-gray and gray-to-binary code converter circuit in a single layer to increase efficiency and reduce complexity. The fault-tolerance performance of the suggested circuits against cell omission, misalignment, displacement, and extra cell deposition faults has significantly improved. Concerning the generalized design metrics of QCA circuits, the fault-tolerance designs have been contrasted with the existing structures. The proposed fault-tolerance circuits' energy dissipation findings have been calculated using the precise QCADesigner-E power estimator tool. Using the QCADesigner-E program, the proposed circuits' functionality has been confirmed. The results implied the high efficiency and applicability of the proposed designs.

Hybrid Quantum-Dot Cellular Automata Nanocomputing Circuits

Quantum-dot cellular automata (QCA) is an emerging transistor-less field-coupled nanocomputing (FCN) approach to ultra-scale ‘nanochip’ integration. In QCA, to represent digital circuitry, electrostatic repulsion between electrons and the mechanism of electron tunnelling in quantum dots are used. QCA technology can surpass conventional complementary metal oxide semiconductor (CMOS) technology in terms of clock speed, reduced occupied chip area, and energy efficiency. To develop QCA circuits, irreversible majority gates are typically used as the primary components. Recently, some studies have introduced reversible design techniques, using reversible majority gates as the main building block, to develop ultra-energy-efficient QCA circuits. However, this approach resulted in time delays, an increase in the number of QCA cells used, and an increase in the chip area occupied. This work introduces a novel hybrid design strategy employing irreversible, reversible, and partially reversible QCA gates to establish an optimal balance between power consumption, delay time, and occupied area. This hybrid technique allows the designer to have more control over the circuit characteristics to meet different system needs. A combination of reversible, irreversible, and innovative partially reversible majority gates is used in the proposed hybrid design method. We evaluated the hybrid design method by examining the half-adder circuit as a case study. We developed four hybrid QCA half-adder circuits, each of which simultaneously incorporates various types of majority gates. The QCADesigner-E 2.2 simulation tool was used to simulate the performance and energy efficiency of the half-adders. This tool provides numerical results for the circuit input/output response and heat dissipation at the physical level within a microscopic quantum mechanical model.

Quad-functioning parity layout for nanocomputing: A QCA design

Quantum dot cellular automata (QCA) is considered an alternative to conventional technologies like CMOS (Complementary Metal-Oxide-Semiconductor) technology due to its potential for lower power consumption, higher speed, and increased device density. QCA introduces a novel approach to designing nano communication circuits and systems. Nano communications data mistakes are detected via parity generators and checkers. The parity bit of each data block ensures that the number of 1′s is either even or odd. Consequently, the system requires four circuits: an even parity generator, an odd parity generator, an even parity checker, and an odd parity checker. The whole system requires more space and cell complexity. In this work, we propose a QCA architecture that serves as a generator for both even and odd parities, as well as a checker for both even and odd parities. It is a quad-functioning circuit that performs four distinct operations within a single design, utilizing 118 QCA cells and occupying an area of 0.17 μm2. The recommended approach uses an efficient XOR gate, resulting in improvements across several performance metrics. QCAPro calculates energy dissipation and design parameters. The recommended QCA circuit outperformed similar QCA circuits in size, complexity, and energy dissipation. The circuit's design cost functions are also low. There has been a 17% reduction in latency and an 86% improvement in QCA-specific costs when compared to the optimal existing design. Moreover, it necessitates a 40% reduction in majority gate usage. The proposed design may compete effectively with other equivalent higher-order circuit designs by reducing the need for multiple blocks in conventional circuits to execute the same task. This architecture holds potential benefits for nano processors and nano communication networks.

Design of QCA based memory cell using a novel majority voter with physical validation

Quantum Dot Cellular Automata (QCA) is a unique transistor less paradigm which effectively uses change in cell polarization to perform logical operations with high speed, low power and high intricacy. In recent years, the need of high performance memory cell is increased for improving the system performance. This paper presents the design of a QCA based memory cell with read write capabilities. In recent past, most of the QCA circuits are designed using the conventional three input majority voter. The conventional three input majority gate is not fault tolerant. Thus, we need an alternative design which can serve as the majority voter and also shows the fault tolerance. Moreover, the design of three input majority voter is not much addressed . In this paper, an alternative, simple structure of three input majority voter is presented which is better than the conventional one in terms of fault tolerance. In addition to this, the proposed three input majority voter is power aware and efficient to realize various digital circuits. The correctness of the proposed majority voter is validated through the physical proof. Moreover, the proposed gate is subjected to cell displacement defect to investigate the testability. The proposed gate is further used to implement rudimentary elements such as XOR gate, multiplexer and D latch. Finally, the design of Random Access Memory (RAM) cell with read, write, set and reset capabilities is proposed using the presented majority voter. The proposed circuits are further subjected to comprehensive analyses for estimation of cost functions and energy dissipation. The investigation of presented circuits manifests the use of proposed majority voter for next generation computing circuits.

A review on regular clocking scheme in quantum dot cellular automata

Quantum-dot cellular automata (QCA) is a novel and emerging nanotechnology that explores the potential of using quantum dots as information carriers in computing devices. The information transfer, as well as timing synchronization of the QCA circuit, is controlled by clocks. Despite this, most of the work done in QCA does not consider the proper layout of the underlying clocking circuit required. Hence, it ends up with QCA circuits with irregular clock zones, which is not suitable for fabrication. However, for efficient design and to provide proper routing options within the clock zones, a regular, scalable clocking scheme is needed. Without a well-defined and regular clocking zone, the QCA circuit designs are incomplete and not a standard fabrication candidate. In this regard, several regular clocking schemes in QCA are discussed in the literature. In this survey, a systematic review of those clocking schemes will be investigated. A detailed comparison of these schemes is also discussed based on design architecture and fabrication point of view.

An Efficient Design of 2-BIT Arithmetic Logical Unit in Quantum Dot Cellular Automata

For the past two decades, CMOS technology has reigned supreme in the world of Very Large Scale Integration (VLSI). But Quantum Dot Cellular Automata (QCA) is stepping into the spotlight, offering a fresh solution to the growing challenges of CMOS. This paper delves into the potential of QCA circuits by presenting a 2-bit Arithmetic Logic Unit (ALU) crafted with this groundbreaking technology, while also benchmarking it against conventional CMOS designs. The proposed QCA-based ALU delivers a trifecta of benefits: streamlined circuit design, exceptional space efficiency, and reduced quantum cost—all while keeping performance sharp in terms of latency and area usage. This 2-bit ALU encompasses a suite of operations: addition, subtraction, multiplication, division, bitwise AND, OR, XOR, and XNOR. QCA technology addresses some of CMOS's major pain points, like slow switching speeds, and doesn't require additional power sources, making it both efficient and environmentally friendly. This is not just an incremental improvement; it's a bold leap into the future of circuit design

An Ultra-Energy-Efficient Reversible Quantum-Dot Cellular Automata 8:1 Multiplexer Circuit

Energy efficiency considerations in terms of reduced power dissipation are a significant issue in the design of digital circuits for very large-scale integration (VLSI) systems. Quantum-dot cellular automata (QCA) is an emerging ultralow power dissipation approach, distinct from traditional, complementary metal-oxide semiconductor (CMOS) technology, for building digital computing circuits. Developing fully reversible QCA circuits has the potential to significantly reduce energy dissipation. Multiplexers are fundamental elements in the construction of useful digital circuits. In this paper, a novel, multilayer, fully reversible QCA 8:1 multiplexer circuit with ultralow energy dissipation is introduced. The power dissipation of the proposed multiplexer is simulated using the QCADesigner-E version 2.2 tool, describing the microscopic physical mechanisms underlying the QCA operation. The results show that the proposed reversible QCA 8:1 multiplexer consumes 89% less energy than the most energy-efficient 8:1 multiplexer circuit previously presented in the literature.

Notice of Violation of IEEE Publication Principles: Design of Cost Efficient Modular Digital QCA Circuits using Optimized XOR Gate

Notice of Violation of IEEE Publication Principles “Design of Cost Efficient Modular Digital QCA Circuits using Optimized XOR Gate” by Suhaib Ahmed and Syed Farah Naz in IEEE Transactions on Circuits and Systems II: Express Briefs After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE’s Publication Principles. This paper contains significant portions of original text from the paper cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission. “Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata” By Haotian Chen, Hongjun Lv, Zhang Zhang, Xin Cheng and Guangjun Xie in Journal of Circuits, Systems, and Computers, Vol. 28, No. 8, 2017 The advantages such as high operating frequency (in the range of few THz), low power dissipation, small size and high density in the nano regime has led to the application of Quantum dot Cellular Automata (QCA) in designing various digital circuits. In this brief, an ultra-efficient two input XOR gate design in QCA is proposed. It is a single layer design consisting of only 9 cells with no crossover and operating on cell to cell interaction. The functionality of the proposed gate has been verified at both physical and simulation level. In addition to this, fault tolerance to single cell missing defect, single cell addition defect and single cell displacement defect of the proposed XOR gate has also been presented. Based on the performance evaluation, it is seen that the proposed XOR gate has least cell count, least area and least latency which in turn leads to least circuit cost. Also, the proposed design dissipates least energy. The applicability of proposed XOR gate has also been investigated by designing various cost efficient digital circuits such as full adder, parity checker, etc.

A thermally aware performance analysis of quantum cellular automata logic gates

<span lang="EN-US">The high-performance digital circuits can be constructed at high operating frequency, reduced power dissipation, portability, and large density. Using conventional complementary-metal-oxide-semiconductor (CMOS) design process, it is quite difficult to achieve ultra-high-speed circuits due to scaling problems. Recently quantum dot cellular automata (QCA) are prosed to develop logic circuits at atomic level. In this paper, we analyzed the performance of QCA circuits under different temperature effects and observed that polarization of the cells is highly sensitive to temperature. In case of the 3-input majority gate the cell polarization drops to 50% with an increase in the temperature of 18 K and for 5 input majority gate the cell polarization drops more quickly than the 3-input majority. Further, the performance of majority gates also compared in terms of area and power dissipation. It has been noticed that the proposed logic gates can also be used for developing simple and complex and memory circuits.</span>

Programmable Synchronous 2-Bit Counter in Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is a newly-developed nanoscale electron device that has the potential to replace the conventional transistor in the future. Owing to the unique field-coupling mechanism of QCA, several constraints must be fulfilled during the design of QCA sequential circuits, which makes the construction of sequential circuits a relatively intractable issue in QCA research. In this paper, a programmable synchronous 2-bit counter in QCA is proposed, which is consisted of combinational logic and falling edge-triggered JK flip-flops. The count mode of the programmable counter can be changed on-demand by mode control signals. Moreover, an initial state setting method of the QCA circuit is also proposed during the design of the counter so that the effects of random initial states can be avoided. Simulation with QCADesigner software demonstrates the validity of the proposed counter.

Reversible Quantum-Dot Cellular Automata-Based Arithmetic Logic Unit.

Quantum-dot cellular automata (QCA) are a promising nanoscale computing technology that exploits the quantum mechanical tunneling of electrons between quantum dots in a cell and electrostatic interaction between dots in neighboring cells. QCA can achieve higher speed, lower power, and smaller areas than conventional, complementary metal-oxide semiconductor (CMOS) technology. Developing QCA circuits in a logically and physically reversible manner can provide exceptional reductions in energy dissipation. The main challenge is to maintain reversibility down to the physical level. A crucial component of a computer's central processing unit (CPU) is the arithmetic logic unit (ALU), which executes multiple logical and arithmetic functions on the data processed by the CPU. Current QCA ALU designs are either irreversible or logically reversible; however, they lack physical reversibility, a crucial requirement to increase energy efficiency. This paper shows a new multilayer design for a QCA ALU that can carry out 16 different operations and is both logically and physically reversible. The design is based on reversible majority gates, which are the key building blocks. We use QCADesigner-E software to simulate and evaluate energy dissipation. The proposed logically and physically reversible QCA ALU offers an improvement of 88.8% in energy efficiency. Compared to the next most efficient 16-operation QCA ALU, this ALU uses 51% fewer QCA cells and 47% less area.

Defects of quantum dot cellular automata computing devices: An extensive review, evaluation, and future directions

Quantum dot cellular automata (QCA), a nanoscale technology, are more prone to faults due to their diminutive size and precise fabrication process. The defects of QCA circuits have been the topic of many research papers, and this work has conducted a comprehensive study of the defect characterisation of QCA circuits. In this work, the defects in QCA circuits are divided into four groups: faults in the synthesis phase, faults in the deposition phase, faults in the design phase, and other faults. In addition, some unusual defects, such as stuck-at faults and single electron faults, are looked at. The study of the existing QCA works shows that fault-tolerant wires, tiles, etc. are rarely discussed in the literature. The literature also lacks adequate explanations of the QCA fault-tolerant clocking mechanism and fabrication processes. This work describes the identified challenges as well as their possible solutions. Additionally, this article outlines the future direction of this research and any relevant constraints. As a result, the intended audience can have a holistic understanding of the faults associated with QCA. This effort also seeks to facilitate the understanding of QCA circuit defects by related researchers.

A unique universal block in QCA technology

The limitations of Complementary Metal Oxide Semiconductor (CMOS) such as high-power dissipation, short channel effects, and high lithography has prompted scientists to look forward to alternatives. Many nanotechnologies were emerged and still in the competition such as Fin Field-Effect Transistor (FinFET), Carbon Nanotube Field-Effect Transistor (CNFET), Quantum-dot Cellular Automata (QCA). QCA is a new nanoelectronics technology used a new method for calculations and it is a promising technology in terms of power dissipation. In QCA, circuit complexity is depending on cell count, area and latency. For commercial purposes a universal gate is necessary, this gate can be used alone to design any Boolean function, where in CMOS technology, the NAND or NOT gates have the ability to be a universal gate. The dominant gates in QCA are the majority gate with inverter where QCA circuits cannot be designed using only a universal gate. Because the structure of the gate is important in QCA, this paper introduces a new low complexity singular block that can be used as a universal block. The proposed block can be used to form AND, OR, NOT, Exclusive-OR (XOR) and Multiplexer (MUX). So, this block not just used to design any circuit but also it can be used to form other important functions XOR and MUX to build large circuits in an optimum form.

An ultra-efficient design of fault-tolerant 3-input majority gate (FTMG) with an error probability model based on quantum-dots

Quantum-dot cellular automata (QCA) has recently attracted significant notice thanks to their inherent ability to decrease energy dissipation and decreasing area, which is the primary need of digital circuits. However, the lack of resistance of QCA circuits under defects in previous works is a vital challenge affecting the stability of the circuit and output production. In addition, with the high defect rate in QCA, suggesting resistance and stable structures is critical. Furthermore, the 3-input majority gate is a fundamental component of QCA circuits; therefore, improving this essential gate would enable the development of fault-tolerant circuits. This paper recommends a 3-input majority gate which is 100% fault-tolerant against single-cell omission defects. Moreover, the fundamental gates are introduced based on the proposed gate. In addition, an adder and a 1:2 decoder are also designed. Using QCADesigner 2.0.3 and QCAPro software, simulations of structures and analysis of power consumption are performed.

An efficient three-level nano-design for reversible gate using quantum dot-cellular automata with cost analysis

Quantum-dot Cellular Automata (CA) is a suitable nanotechnology for replacing CMOS circuits. The majority, inverter, and reversible structures, are the primary building blocks in quantum-dot CA circuits. Since the reversible gates have recently attained great attention, this paper proposes a new design of a reversible building block based on the Feynman gate. The proposed quantum-dot CA-based Feynman gate is denser and has low delay than the existing circuits. This paper also tests the possible implementation of the proposed design in quantum-dot CA. The QCADesigner is employed to test the functionality of the proposed structure. The proposed efficient quantum-dot CA-based Feynman gate has only 36 cells in three-layer. It consumes 0.03 µm2, which is the smallest among all previous designs. A quantum-cost comparison of the proposed reversible Feynman gate with conventional reversible gates demonstrates the cost-effectiveness of quantum-dot CA. The simulation result matched the truth table of the Feynman gate, indicating that the suggested quantum-dot CA architecture is functional. The proposed architecture can also be used for n-bit code converters as well.