Adder In Quantum-dot Cellular Automata Research Articles

Efficient co-planar adder designs in quantum dot cellular automata: Energy and cost optimization with crossover elimination

Quantum dot cellular automata (QCA) stands as a highly promising nanotechnology, capable of outperforming conventional CMOS technology. Leveraging its advantages, this paper addresses the challenges in adder circuits related to size, delay, and cost by integrating QCA technology. A novel layout for a co-planar full adder in QCA is introduced, featuring a half-adder design with 23 cells in a single layer without any crossover, achieving a delay of 0.25 clock cycles. By utilizing inter-cellular effects inherent in QCA technology, the presented designs offer significant improvements in a variety of design metrics, and a cost efficiency of 64.3%, distinguishing them from traditional logic design approaches. Additionally, in order to ensure an efficient routing channel and a consistent structure of the adder design, a Universal, Scalable, and Efficient (USE) clocking scheme has also been employed. The adder design is further used to build 4-bit and 8-bit Ripple Carry Adders. An extensive study on energy dissipation using QCADesigner-E and QCAPro tools is conducted for three tunneling energies (0.5 Ek, 1 Ek, and 1.5 Ek). The full adder design showcases substantial improvement in energy to delay cost when compared to the closest reported design, achieving improvements of 91.66%, 89.03%, and 88% at 0.5 Ek, 1 Ek, and 1.5 Ek, respectively. The results highlight enhanced circuit efficiency and streamlined layouts, outperforming existing models and offering substantial benefits to high-performance and energy-efficient computing systems.

Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata

<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Editor’s notes:</i> Quantum-dot cellular automata (QCA), as one of the proposed improvements on conventional CMOS, has its own reliability challenges. In this work, a majority-logic-based self-checking feature is proposed as an addition to adders in QCA to increase fault tolerance. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">—Fei Su, Intel</i>

An efficient QCA-based full adder design with power dissipation analysis

ABSTRACT Quantum Dot-Cellular automata (QCA) is a developing technology that is considered as the best viable alternate solution for CMOS technology which has short-channel effects. QCA is a transistor-free technology, and the information is distributed formulated on the charge of the electron and by Columbic repulsion theory. In this paper, an optimal adder circuit is proposed using QCA technology which consist only 14 cells. The proposed adder circuit is further utilised for designing of 4-bit adder design efficiently. Simulations results, are obtained precisely using QCADesigner software version 2.0.3., confirm that the proposed circuits work well. Moreover, the energy dissipations of the proposed adder circuit design is estimated using QCAPro tool. The performance of the proposed design was compared with the existing ones which shows better performance in terms of cell count, area, and latency. Suggested 1-bit and 4-bit QCA adders exhibit a delay of 0.5 and 1.25 clock cycle, occupy an active area of 0.01 and 0.1 and μm2, and use 14 and 84 QCA cells, respectively.

Ultra-efficient adders and even parity generators in nano scale

This paper suggests a single-layer 5-input majority gate (MV5) using 11 simple cells in the Quantum-Dot Cellular Automata (QCA) technology. All simulations are performed by QCADesigner 2.0.03. Moreover, the energy consumption of the suggested 5-input majority gate is calculated using the QCAPro tool. The suggested gate shows power consumption improvements by 15.69, 9.56, and 5.95% at three levels of 0.5Ek, 1Ek, and 1.5Ek compared with the best previous designs. Moreover, using the suggested gate, n-bit QCA adder and n-bit even parity generator are designed. A comparison of the cell counts in the suggested 1-bit full-adder and the 4-bit even parity generator with the best previous structures shows 35.21% and 6.12% improvements, respectively. In addition, the suggested 4-bit and 8-bit adders show 2.29%, 4.87%, 5.76% and 24.29% improvements in terms of the cell counts compared to the best designs, respectively.

CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability

The significant physical challenges of Complementary Metal Oxide Semiconductor (CMOS) technology drives it on the brink of ultimate limit. With the surfacing of tremendous research findings, Quantum dot cellular automata (QCA) has emerged as a new technology in nanoscale era as a viable alternative to CMOS technology. Besides its wide acceptance, QCA-based nanoscale circuits are highly susceptible to huge fault/error rates. Thus, the fault tolerance and testability have become the utmost necessity for ensuring reliable QCA circuit. Toward this direction, conservative logic plays a vital role to achieve such reliability. In this paper, a Conservative Full Adder (CFA) is proposed with a simplified testable logic to detect the internal fault in the circuit. A simple majority–minority-based testing logic in the circuit is augmented for the detection of conservative (bit preserving) nature. Besides the testable feature, the full adder is chosen for its versatility in Arithmetic and Logic Unit (ALU) synthesis. Experimental result establishes the superiority of the proposed logic in terms of design capability as well as testability. Also, a comprehensive analysis of energy dissipation is performed to ensure the robustness of the proposed testable conservative adder. The QCA layout design and functional verification of the design are performed using the QCADesigner tool and Hardware Description Language for QCA (HDLQ) tool, respectively. The QCAPro simulator is used to evaluate the energy dissipation of the circuit.

Design of reversible universal and multifunctional gate-based 1-bit full adder and full subtractor in quantum-dot cellular automata nanocomputing

The issues faced by CMOS technology in the nanoregime have led to research for other possible technologies that can operate with the same functionalities but with higher speed and lower power dissipation. One such technology is quantum-dot cellular automata (QCA). A 3 × 3 reversible universal and multifunctional gate is presented that is reversible, universal, and multifunctional in nature. The gate is then used as a building block to design an ultra-efficient 1-bit full adder and 1-bit full subtractor in QCA. Based on the performance analysis, it is concluded that the proposed designs are efficient in respect to cell count, area, delay, and quantum cost and achieve performance improvements over existing designs in the literature. Hence, the proposed designs can be efficiently utilized in various digital logics requiring minimal area and ultra-low-power consumption such as central processing units, microcontrollers, etc.

A unique three-layer full adder in quantum-dot cellular automata

Unlike previous technologies, QCA does not depend on the movement of electrons in the wire to transmit information. This feature significantly improves the speed of the circuits and reduces the power consumption, which is a great incentive for digital circuit designers to use this technology. In this paper, a new structure of full-adder is proposed, designed, implemented and simulated using two gates that improve the complexity and latency compared to previous designs. Simulation results are obtained using QCADesigner which illustrates the valid performance of the proposed design. The proposed structure has a 30% improvement in the number of cells and a 41% improvement in the occupied area.

Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata

A multiplier is one of the main units for digital signal processing and communication systems. In this paper, a high speed and low complexity multiplier is designed on the basis of quantum-dot cellular automata (QCA), which is considered promising nanotechnology. We focus on Vedic multiplier architectures according to Vedic mathematics from ancient Indian sculptures. In fact, an adder is an important block in the design of almost all types of multipliers and a ripple carry adder is used to design simple multiplier implementations. However, a high-speed multi-bit multiplier requires high-speed adder owing to carry propagation. Cell-interaction-based QCA adders have better improvements over conventional majority-gate-based adders. Therefore, a two-bit Vedic multiplier is proposed in QCA and it is used to implement a four-bit form of the multiplier. The proposed architecture has a lower cell count and area compared to other existing structures. Moreover, simulation results demonstrate that the proposed design is sustainable and can be used to realize complex circuit designs for QCA communication networks.

Reliable coplanar full adder in quantum-dot cellular automata using five-input majority logic

Quantum-dot cellular automata (QCA) is an evolving technology to design circuits at nanometer levels. Most of the digital systems have an adder integrated in the circuit. Circuits in QCA are implemented using majority gates. Most of the existing adder designs are implemented using majority logic and exclusive-or logic. The circuits in QCA are prone to fabrication defects that can affect the performance of the circuit drastically. Missing cell defect is crucial among them. In this work, the existing gates used to implement the adders are analyzed, and a reliable clock zone full adder is proposed using the better fault tolerant gate. The proposed adder is more reliable since both the Sum and Carry are generated by reliable gates. Missing cell defect analysis and design validation are carried out using QCADesigner. The proposed design has fewer cells and more reliability compared to the designs which have considered reliability as an important factor to design adders.

Cost-efficient full adder designs in quantum-dot cellular automata

Quantum-dot cellular automata has all the vital characteristics needed by a post-complementary metal oxide semiconductor technology. Adder is a key constituent in any digital circuit system. Several full adder designs are proposed in quantum-dot cellular automata. The different existing techniques used in quantum-dot cellular automata adders are analysed in this work and two cost-efficient full adder designs are proposed using different crossover techniques. The proposed designs have minimum cells and are faster compared to the adders in the literature. They also have the ability to be extended to realise adders of any word length. Missing cell defect analysis is done for the proposed designs and compared with the other adder designs. The designs are validated using QCADesigner.

Cost-efficient full adder designs in quantum-dot cellular automata

Quantum-dot cellular automata has all the vital characteristics needed by a post-complementary metal oxide semiconductor technology. Adder is a key constituent in any digital circuit system. Several full adder designs are proposed in quantum-dot cellular automata. The different existing techniques used in quantum-dot cellular automata adders are analysed in this work and two cost-efficient full adder designs are proposed using different crossover techniques. The proposed designs have minimum cells and are faster compared to the adders in the literature. They also have the ability to be extended to realise adders of any word length. Missing cell defect analysis is done for the proposed designs and compared with the other adder designs. The designs are validated using QCADesigner.

A combined three and five inputs majority gate-based high performance coplanar full adder in quantum-dot cellular automata

Nowadays, arithmetic computing is an important subject in computer architectures in which the one-bit full-adder gate plays a significant role. Thus, efficient design of such full-adder component can be beneficial to the overall efficiency of the entire system. In this essay, a novel method for the design and simulation of a combined majority gate toward realization of the one-bit full-adder gate is proposed. We inspect an alternative approach for the streamlined physical design of quantum-dot cellular automata (QCA) full-adder circuits in which the placement of input cells and wire crossing congestion are substantially reduced. The proposed method has outstanding characteristics such as low complexity, reduced area consumption, simplified physical design, and ultra-high speed one-bit full-adder. Based on simulation results the proposed design provides 33.33% reduction in area and 20.00% improvement in complexity as well as 10.49% in 1 Ek reduction in power consumption.

Design of Ultra-Efficient Reversible Gate Based 1-bit Full Adder in QCA with Power Dissipation Analysis

The difficulties which the CMOS technology is facing at the nano scale has led to the investigation of quantum-dot cellular automata (QCA) nanotechnology and reversible logic as an alternative to conventional CMOS technology. In this paper, these two paradigms have been combined. Firstly, a new 3 × 3 reversible gate, SSG-QCA, which is universal and multifunctional in nature, is proposed and implemented in QCA using conventional 3-input majority voter based logic. By using the concept of explicit interaction of cells, the proposed gate is further optimized and then used to design an ultra-efficient 1-bit full adder in QCA. The universal nature has been verified by designing all the logic gates from the proposed SSG-QCA gate whereas the multifunctional nature is verified by implementing all the 13 standard Boolean functions. The proposed 3 × 3 gate and adder designs are then extensively compared with the existing literature and it is observed that the proposed designs are ultra-efficient in terms of both area and cost in QCA technology. In addition to this energy dissipation analysis for different scenarios is also done on all the designs and it is observed that the proposed designs dissipate minimum energy thereby making them suitable for ultra-low power designs.

New designs of fault-tolerant adders in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology has attracted attention as one of the best forms of alternative Nanoscale CMOS technology. It has facilitated the designing of digital circuits with high density and speed. One of the important issues in QCA technology is designing fault-tolerant digital circuits. QCA-based circuits frequently suffer from fabrication and unstable faults: these make them unreliable and susceptible to breakdown. In this paper, two new fault-tolerant 3-input majority gates have been proposed in QCA technology. The robustness of the proposed structures has been evaluated in terms of defects such as cell omission, deposition of extra cell and cell displacement defects. The simulations were performed using the QCA Designer 2.0.03 and QCAPro tools to measure performance and energy consumption. The obtained results indicate that the proposed structures benefit from higher fault-tolerant in comparison to previous designs. Moreover, we provided four new fault-tolerant full-adders and a multi-bit adder using the proposed structures and acceptable results are archived.

Design and analysis of efficient QCA reversible adders

Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS technology. In a QCA structure, information destruction plays an essential role in the overall heat dissipation, and in turn in the power consumption of the system. Therefore, reversible logic, which significantly controls the information flow of the system, is deemed suitable to achieve ultra-low-power structures. In order to benefit from the opportunities QCA and reversible logic provide, in this paper, we first review and implement prior reversible full-adder art in QCA. We then propose a novel reversible design based on three- and five-input majority gates, and a robust one-layer crossover scheme. The new full-adder significantly advances previous designs in terms of the optimization metrics, namely cell count, area, and delay. The proposed efficient full-adder is then used to design reversible ripple-carry adders (RCAs) with different sizes (i.e., 4, 8, and 16 bits). It is demonstrated that the new RCAs lead to 33% less garbage outputs, which can be essential in terms of lowering power consumption. This along with the achieved improvements in area, complexity, and delay introduces an ultra-efficient reversible QCA adder that can be beneficial in developing future computer arithmetic circuits and architectures.

Efficient design of coplanar ripple carry adder in QCA

An optimal quantum-dot cellular automata (QCA) design for full adder (FA) based on an optimal three-input exclusive-OR (XOR) gate is presented. This XOR structure utilises a new configuration of cells unlike traditional gate-level approaches. The coplanar QCA FA spans over and delays of 0.5 clock cycles with 40 cells. It achieves total energy dissipation as low as 0.144 eV at 1.5 energy level. The utility of proposed gate is leveraged to design a ripple-carry adder (RCA) as a specific application. For performance evaluation, the authors use traditional cost metrics and QCA-specific cost function. Results show that proposed n -bit RCA outperforms most of the best state-of-the-art designs known in the literature. For example, cell count (area consumption) of 4, 8, and 16 bit adders is 62% (70%), 66% (84%), and 70% (86%) less than the best coplanar RCA design results. In addition, by taking the new cost metrics into account, it is found that proposed adder performs fairly well as compared to the previous adders too. These designs are realised and simulated using QCADesigner.

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing

The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.

Design of Efficient BCD Adders in Quantum-Dot Cellular Automata

Among the emerging technologies recently proposed as alternatives to the classic CMOS, quantum-dot cellular automata (QCA) is one of the most promising solutions to design ultralow-power and very high speed digital circuits. Efficient QCA-based implementations have been demonstrated for several binary and decimal arithmetic circuits, but significant improvements are still possible if the logic gates inherently available within the QCA technology are smartly exploited. This brief proposes a new approach to design QCA-based BCD adders. Exploiting innovative logic formulations and purpose-designed QCA modules, computational speed significantly higher than existing counterparts is achieved without sacrificing either the occupied area or the cell count.

Radix-8 full adder in QCA with single clock-zone carry propagation delay

We design a 3-bit adder or a radix-8 full adder (FA) in quantum-dot cellular automata (QCA), where the 3-bit carry propagation path can be accommodated in one clock-zone. To achieve this, we introduce group majority signals similar to group propagate and generate signals in parallel prefix computations, use them to reformulate the carry expressions of a previous radix-4 FA, and as such we could extend it to higher radix FAs. Applying the aforementioned new interpretation of carry expressions (via group majority signals) on 3-bit adders, results in that only a single clock cycle is required for 12-bit (vs. the previous 8-bit) carry propagation, across four radix-8 FAs. Based on the proposed radix-8 QCA-FA, we realized 8-, 16-, 32-, 64, and 128-bit QCA adders via QCADesigner. Comparison of these adders with the previous radix-4 experiment, showed 9–41% speed up, and 57–76% area saving, for 16–128-bit adders, respectively. On the other hand, compared to the best previous radix-2 design, for the same bit widths, we experienced 57–172% speed up, but at the cost of 138–4% area increase, except for the 64 and 128-bit cases, where we also experienced 19% and 41% area saving, respectively.

Design of Testable Adder in Quantum‐dot Cellular Automata with Fault Secure Logic

The rapid advancement of Quantum-dot cellular automata (QCA) technology has moved on to the effective methods for testing these circuits due to its insufficient reliability. The growing demand for fault tolerance and testability attracts more research on it. This paper targets, a novel parity preserving testable adder (t-Adder) in QCA which tackles the internal fault within the gate efficiently resulting a testable circuit. The fault patterns of t-Adder gate under cell deposition defects are investigated. The most striking characteristic of this logic is that it is completely testable for single as well as multiple stuck-at faults using only three test vectors. Also, the functionality and the defect tolerance of the proposed t-Adder under the Path Fault Secure (PFS) scheme are studied which ensures more reliability. A comprehensive power dissipation analysis, as well as structural analysis of the testable logic gates, is performed which signifies the dominance of t-Adder in low power consumption. Further, the programmable feature of t-Adder is utilized to implement an efficient ALU, realizing 10 important functions along with addition operation. The design of QCA layout, as well as functional verification of the proposed design, is performed using the QCADesigner and HDLQ tool respectively whereas the power dissipation is evaluated using QCAPro simulator.