Quad Flat Package Research Articles

Study of delaminated plastic packages by high temperature Moire and finite element method

In the current study, 1200 l/mm gratings are replicated at elevated temperatures onto the cross sections of two delaminated plastic packages: a thin quad flatpack plastic package (TQFPP) and a power small outline plastic package (PSOPP). The specimens are measured at room temperature for thermal deformation induced by cooling process. The finite element models are used to simulate the cooling process and the results are compared with the Moire interferometry results. The finite element models with different delaminations between die and die attach are used to simulate the fringe patterns obtained from Moire interferometry. It was found that the delamination size can be estimated by the combination of Moire technique and finite element method. The finite element model, once verified, can then be used in making cost effective decisions in plastic packaging design and processing.

A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor

This paper describes a 160 MHz 500 mW 32 b StrongARM(R) microprocessor designed for low-power, low-cost applications. The chip implements the ARM(R) V4 instruction set and is bus compatible with earlier implementations. The pin interface runs at 3.3 V but the internal power supplies can vary from 1.5 to 2.2 V, providing various options to balance performance and power dissipation. At 160 MHz internal clock speed with a nominal Vdd of 1.65 V, it delivers 185 Dhrystone 2.1 MIPS while dissipating less than 450 mW. The range of operating points runs from 100 MHz at 1.65 V dissipating less than 300 mW to 200 MHz at 2.0 V for less than 900 mW. An on-chip PLL provides the internal clock based on a 3.68 MHz clock input. The chip contains 2.5 million transistors, 90% of which are in the two 16 kB caches. It is fabricated in a 0.35-/spl mu/m three-metal CMOS process with 0.35 V thresholds and 0.25 /spl mu/m effective channel lengths. The chip measures 7.8 mm/spl times/6.4 mm and is packaged in a 144-pin plastic thin quad flat pack (TQFP) package.

Assembly and Reliability of Very Large Flip‐chip on CQFP

The IBM ceramic quad flat pack (CQFP) is a high performance, low‐cost chip carrier for surface mount assembly. It is an extension of metallised ceramic (MC) and metallised ceramic with polyimide (MCP) product technologies. These finished modules conform to JEDEC I/O and footprint standards. They are available in 0.5 mm and 0.4 mm lead pitches with flexibility to address unique application requirements such as body sizes or lead pitches. Connection from integrated circuit (IC) to carrier is performed using flip‐chip (C4 ‐ Controlled Collapse Chip Connection) attach. Silicon die size and the quantity of C4 connections for flip‐chip joining have historically been constrained to reduce early life failures caused by solder fatigue wearout. This DNP (distance from neutral point of chip footprint) limitation has been overcome with increasing usage of epoxy encapsulation as a flip‐chip underfill. The encapsulant matches the coefficient of thermal expansion (CTE) of C4 solder and minimises stresses on the interconnection. This enhancement provides a substantial reliability improvement in comparison with unencapsulated packages. Also, it enables larger die with smaller C4 solder bumps on finer pitches to be assembled on ceramic carriers. Recent product development and testing have extended flip‐chip on ceramic packaging technology even further than previously anticipated. Test die up to 20 mm in size with over 2,000 C4 joints have been successfully assembled, encapsulated, stress tested and qualified in CQEP modules. Flip‐chip assembly and encapsulation of C4 connections on very large die to CQFP components have been implemented into IBM manufacturing production. This large‐scale packaging enhancement continues to demonstrate that flip‐chip underfill eliminates the intrinsic failure mechanisms associated with fatigue wearout. This provides a significant technology extension to this low‐cost and high reliability product offering.

APPLICATION OF PHASE CHANGE MATERIALS FOR PASSIVE THERMAL CONTROL OF PLASTIC QUAD FLAT PACKAGES: A COMPUTATIONAL STUDY

Abstract A transient three-dimensional analysis was performed for passive thermal control of a plastic quad flat package by incorporating an organic phase change material (PCM) under the printed wiring board. Governing conservation equations for mass, momentum, and energy were solved by an implicit finite volume numerical technique. The effects of phase change were modeled by a single-domain enthalpy-porosity technique. To study the effects of thermal conductivity of the board, a total of six cases were considered with two different board materials. It was found that passive cooling with PCM can arrest the temperature rise for substantial time, for the power levels considered. A higher board thermal conductivity resulted in a reduction in temperature levels. The melt region for a lower thermal conductivity of the board was found to be localized near the package footprint, while for a higher board conductivity, the melt region extends along the board.

EXPERIMENTAL STUDY OF SOLDER JOINT RELIABILITY IN A 256 PIN, 0.4 MM PITCH PQFP

A no-clean surface mount process for the assembly of Plastic Quad Flat Packs (PQFPs) with 15.7 mil (0.4 mm) pitch and 256 leads was established. The reliability of solder joints was assessed through accelerated life-time testing method. Samples were tested under a temperature cycling range of between –55°C and 125°C to study the microstructure change and fatigue life of solder joints. Observations of microstructure changes such as the growth of intermetallics, grain coarsening as well as thermal fatigue cracks were made. The cracks were seen to initiate particularly at heel and toe fillet regions of solder joints. The temperature cycling test results were then modeled by Weibull distribution, and the reliability and failure rate functions for the current surface mount solder joint process were determined. Under the temperature cycling test condition, the mean time to failure of the assembly was 7327 cycles. If operating under a temperature range of between 23° C and 99° C with one cycle per day, about 50% of the PQFPs were predicted to survive for about 15,753 cycles, or approximately 43 years.

FLOW MODELING OF PQFP DURING TRANSFER MOLDING

This paper addresses the use of Finite Element Method (FEM) and Finite Difference Method (FDM) for flow modeling of plastic quad flat package (PQFP) during automated transfer molding. The use of such numerical methods, together with the analytical model, can predict accurately the filling profile, melt-front advancement and wire sweep of PQFP during the molding process. This work adopted a more utilitarian engineering assumption for the flow modeling of the molding process compared with other published work. Factors considered for the prediction are the ram-speed profile for filling and melt front advancement, while for wire sweep the die and basic leadframe structure are included. With these improved assumptions the numerical results obtained for filling, melt front advancement and wire sweep agree well with experimental measurements. Also, a Sweep Indicator (SWI) model is developed that indicates potential zones of extensive wire sweep. This improved modeling methodology can lead to better and more cost-effective designs of molds used for encapsulation of plastic integrated circuits. Such use of computer aided engineering (CAE) helps to address reliability problems such as wire sweep in integrated circuits before production. It allows for process optimization of the molding parameters.

Ground noise minimization in integrated circuit packages through pin assignment optimization

Due to suboptimal assignment of pins to grounds and signals, the ground noise problem in integrated circuit (ICs) packages either persists or compromises the design by forcing too many pins to be wasted carrying ground reference. This paper proposes a new CAD technique for optimizing pin assignment in IC packages to minimize ground noise using simulated annealing. Optimization techniques are used in which the objective function is the ground noise as determined by simulation of the IC package leadframe. However, modeling and simulation methods currently employed are prohibitively expensive in terms of CPU time. For this reason, two circuit models of the leadframe are developed and used concurrently: one to provide accuracy and the other to ensure fast execution. Using simulated annealing with a ground noise cost function has provided an observed 26-fold reduction in ground noise in a 208-pin IC quad flat pack (QFP) from a poor initial configuration. In addition, the same process was able to produce a 2.2-fold improvement when an intelligent initial pin assignment was used. Furthermore, these results came at a CPU cost of about 1200 s each on a SUN SPARC10 workstation.

Importance of molding compound chemical shrinkage in the stress and warpage analysis of PQFPs

This paper addresses the use of finite element (FE) techniques to predict residual warpage in plastic quad flat packs (PQFPs) after encapsulation. Experimental measurements of package warpage are used to validate FE models of the packages. Failure to incorporate mold compound chemical shrinkage into the FE analysis leads to erroneous predictions of package warpage. The warpage sensitivity of different packages to changes in downset is presented. The validated FE package models predict stress levels in packages which are 70% greater than those with temperature coefficient of expansion (TCE) shrinkage alone and questions the accuracy of previous simulations which do not include molding compound chemical shrinkage.

MCM-L product development process for low-cost MCM's : PARTICK THOMPSON. IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B, 181(1), 9 (February 1995)

System size and cost reduction are often the largest factors for interest in commercial MCMs. Performance improvement is generally of secondary interest. Development and qualification can add significantly to the total cost of an MCM, so in addition to the normal desire to provide reliable products, the cost of doing so has gained increased importance. A new product introduction (NPI) process for low-cost MCMs has been implemented to rapidly provide cost-effective, reliable MCM solutions for cost-sensitive MCM users. The NPI process is based on three attributes: leverage single chip package (SCP) experience and technology, perform product family qualifications, and use only previously qualified silicon in MCMs. Application of the NPI process to the development and qualification of a 28 mm PQFP (Plastic Quad Flat Pack)-based MCM package is presented in this paper. >

Diffusion model to derate moisture sensitive surface mount IC's for factory use conditions

Recent industry specifications JESD22-A112 and IPC-SM-786A have identified a set of moisture sensitivity levels for classification of moisture/reflow sensitive devices. The established test conditions are meant to represent average worst-case factory environmental conditions that a plastic packaged surface mount integrated circuit (IC) can safely be exposed to after opening of the protective dry-bag. The exposure times imposed by the level classifications relate specifically to the equivalent testing condition, e.g., a Level 3 device must be assembled within 168 h for a factory environment of 30/spl deg/C/60% relative humidity (RH). No equivalent exposure times are addressed by the specifications if the factory ambients are not at 30/spl deg/C and 60% RH. This paper addresses the issue of equivalent exposure times for varying temperature-humidity conditions that a factory could maintain. A derating procedure has been developed that adopts a first principles approach for solution to moisture diffusion into plastic packages. One-dimensional and three-dimensional [(1-D) and (3-D)] mathematical and computer-generated solutions for moisture diffusion were obtained for plastic packaged IC's. Critical moisture concentrations, achieved at internal interfaces, during JEDEC/IPC testing conditions were calculated and used as a criterion for the derating procedure. Based on this approach, an equivalency table can be developed for any combination of factory temperature and humidity conditions. Validation of the theoretical predictions was carried out through experiments on two types of plastic packages: a plastic-packaged ball grid array (BGA) and a plastic quad flat pack (PQFP).

Ultra-thin packaging versus the Known Good Die : Keith Gurnett. Microelectronics Journal, 25, 8, xxiii (1994)

An AFM (atomic force microscope) moiré method has been developed to measure surface deformations and strains. The scanning lines in the AFM monitor are used as the reference grating. The reference grating interferes with the specimen grating and forms a moiré pattern on the monitor. The condition of forming scanning moiré with an AFM is described. The deformation measurement principle using AFM moiré is discussed in detail. The AFM moiré method was used to measure the thermal deformations in QFP (quad flat pack) and BGA (ball grid array) packages. The experiment results verify the feasibility of the AFM moiré method and show its ability to measure the in-plane deformations and strains.

A practical lifetime prediction method for inter-poly oxides : Andreas Martin, Paula O'Sullivan and Alan Mathewson. Electron Technology, 27, 1, 55 (Warsaw 1994)

This study investigates the prediction of transient board-mounted electronic component heat transfer in environments representative of reliability screening and surface-mount assembly processes using computational fluid dynamics (CFD) analysis. The test cases are based on a board-mounted 160-lead Plastic Quad Flat Pack (PQFP) component, analysed in still-air and a range of forced airflows. For reliability screening, three types of transient operating conditions are considered, namely (i) component dynamic power dissipation in fixed ambient conditions, (ii) passive component operation in dynamic ambient conditions, and (iii) combined component dynamic power dissipation in varying ambient conditions. For surface-mount assembly, the test vehicle is exposed to a typical solder reflow thermal profile. Benchmark criteria are based on component junction temperature and component-printed circuit board (PCB) surface temperature, measured using thermal test dies and infrared thermography, respectively. Component/PCB numerical modelling is based on nominal geometry dimensions and material properties. Overall, component transient thermal behaviour is found to be accurately predicted, suggesting that CFD analysis could play an important role in providing critical boundary conditions to determine accelerated life testing parameters and optimise new assembly processes.

Fatigue life estimation of surface mount solder joints

A novel and direct method to measure the stress-strain properties of surface mount solder joints is proposed in this paper. The specimen used in the experiments is a quad flat pack (QFP)-solder-printed circuit board (PCB) assembly and the fabrication of solder joints makes use of conventional surface mount technology (SMT). Mechanical cycling and thermal shock testing can be conducted directly on the specimen after assembly. In this manner, the specimen represents practical SMT solder joints in electronic products as far as possible. It is shown that the joint strain and stiffness of chip modules are good evaluation indices to reveal the fatigue status of solder joints. It is further proposed that the criterion of 50% load drop should be used for defining the fatigue life of solder joints. Finally, it is recommended that the total displacement /spl Delta//spl delta//sub 2p/ be used to measure the strain-fatigue life relation for both leaded and leadless joints.

Reliability of metallized ceramic packages

Thin-film circuitization on a dry-pressed alumina ceramic substrate has been a popular approach to developing low-cost ceramic quad flat pack (CQFP) and pin grid array (PGA) packages in the industry. Such material/process sets have also been suggested for simply designed low-cost ball grid array (BGA) packages. Due to the nature of processes involved in manufacturing, and due to handling, these metallized ceramic packages can occasionally possess circuit-line abnormalities. At the present time, all modules with such circuit-line abnormalities are eliminated since they are believed to affect the long-term reliability of the product. The goal of this paper is to understand what impact the circuit-line abnormalities have on the reliability of the metallized ceramic packages. The reliability assessment is carried-out through environmental stress tests correlated with elastic-plastic three-dimensional (3-D) finite element (FE) analyses of idealized circuit line abnormalities. Ninety-three parts with circuit-line abnormalities were thermally cycled between 0/spl deg/C and 100/spl deg/C. Ninety one of these parts survived over 5000 cycles of the test. The FE models showed that the stresses in the circuit lines with abnormalities were mostly elastic over the test temperature range, and so the failure of these circuit lines with abnormalities was governed more by the physics of high-cycle fatigue than by low-cycle fatigue. The tests and models indicate that metallized ceramic substrates are robust under thermal cycling and circuit-line abnormalities caused by manufacturing processes do not reduce the useful life of the product.

Measurement of package inductance and capacitance matrices

A technique is presented for the measurement of resistance, inductance, conductance, and capacitance matrices of large pin count electronic packages. Circuit analysis of an assumed lumped model is used to define a measurement technique based on two sets of measurements on specially prepared samples. Formulas are derived for use with network analyzer measurements. Measurements and simulations on a 208-lead quad flat pack show that the method attains good accuracy for all but the small values of the conductance matrix.

A simultaneous switching noise design algorithm for leadframe packages with or without ground plane

This paper provides design techniques for leadframe packages with or without a ground plane, which enable an accurate estimate of the maximum Simultaneous Switching Noise (SSN) and the required numbers of power and/or ground pins for pre-specified SSN limits early in the design phase. Two heuristic design approaches, namely equal-angle and quarter-plane, are proposed as initial design choices for the lead frame design to meet pre-specified SSN constraint. Effects of the signal conductors in reducing the effective inductance of a leadframe package are quantified. Closed-form equations and SPICE simulation are used to calculate the Simultaneous Switching Noise. A design example for a 28/spl times/28 mm Plastic Quad Flat Package (PQFP) is given to provide guidelines for SSN-constrained design. The design algorithm is integrated into a CAD tool, UASSNS3.0, which is capable of initial SSN design of leadframe packages.

Design of 0.35-mm pitch QFP lead and its assembly technology

The solder joint reliability of a 0.35-mm lead pitch, 42-mm wide/spl times/42-mm long/spl times/23-mm high, 396 pin, ceramic quad flat package (QFP) was studied in terms of: 1) finite element analysis simulation; and 2) temperature cycling tests between -65/spl deg/C and +125/spl deg/C. Using the study results, physical design of the QFP leads, in terms of thickness, standoff, and Au surface finish were optimized. If the von Mises stress of a QFP solder joint can be optimized to be no more 16.7 kilogram square millimeter, we can guarantee QFP solder joint reliability over requested design life. Also, we developed a thermocompression (T/C) soldering process for the QFP. >

Moisture sensitivity and reliability of plastic thermally enhanced QFP packages

Standard plastic quad flat packs have difficulty meeting the thermal performance requirements of devices with high power dissipation. The development of plastic thermally enhanced quad flat packs (TEQFP), which incorporate heat slugs or heat spreaders in the leadframes, provide a cost effective solution. Because the final packages are of molded plastic, TEQFP's are susceptible to moisture-induced cracking and other plastic reliability problems. This paper discusses the impact of moisture on package cracking during the board mounting process and the overall reliability of TEQFP's. Based on our study using scanning acoustic tomography and reliability stress tests, our findings reveal that TEQFP's have comparable reliability to standard PQFP's if proper storage and drying guidelines are followed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

296 lead fine pitch (0.4 mm) thin plastic QFP package with TAB interconnect

The quad flat pack (QFP) package has become the surface mount technology (SMT) package of choice for microprocessors and peripheral devices and is well suited for hand held computer application. To address this market segment Intel has developed a new package with a thin (2.0 mm) body for light weight, low standoff (0.25 mm maximum) for overall lower profile, in a 32 mm/spl times/32 mm body format. Tape automated bonding (TAB) interconnect from die to the leadframe is used to overcome wirebond interconnect limitations. This package provides a more manufacturable package system by using flat handling during test operation. The package is trimmed and formed subsequent to test operation and shipped in standard JEDEC thin matrix plastic trays, ready to use for SMT operation with good lead coplanarity. Package reliability is equivalent to other plastic packages. Sample packages were supplied to selected customers to help develop the 0.4 mm pin pitch SMT process, equipment and materials. The feedback/results indicate that the current base of installed SMT equipment is capable of assembling such 0.4-mm pitch packages with very little or no modification and at acceptable quality levels.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Popcorn phenomena in a ball grid array package

Plastic ball grid array packages can be an alternative to the fine-pitch plastic quad flat package with many I/O's, due to its advantages, such as small footprint and high density interconnect, improved module assembly yield, superior thermal and electrical performances to plastic quad flat packages, etc. In spite of these many advantages, there are several concerns which hinder the plastic ball grid array package from the widespread use. One of them is the package cracking by popcorn phenomena. For the purpose of studying the popcorn phenomena, plastic ball grid array packages with 129 I/O's were tested under the pre-conditioning test conditions. Observations using scanning acoustic tomography and optical microscopy were carried out to investigate the existence of delaminations and cracks in the package, and the cracking patterns after IR reflow. Package deformations and thermomechanical stress distributions in the package were calculated by the finite element method (FEM). Three types of substrates were tried to prove that open thermal viaholes under die pad could prevent popcorn cracking during IR reflow. From the experiments and the observations, it was concluded that package cracking, which was caused by the expansion of moisture concentrated at the die adhesive layer, could be prevented using open thermal viahole under die pad. The open thermal viaholes acted as vent holes, through which the expanded water vapor could escape without causing popcorn cracking. The die-attach process using UV tape was effective in the assembly of the packages with open thermal viaholes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>