Abstract
The IBM ceramic quad flat pack (CQFP) is a high performance, low‐cost chip carrier for surface mount assembly. It is an extension of metallised ceramic (MC) and metallised ceramic with polyimide (MCP) product technologies. These finished modules conform to JEDEC I/O and footprint standards. They are available in 0.5 mm and 0.4 mm lead pitches with flexibility to address unique application requirements such as body sizes or lead pitches. Connection from integrated circuit (IC) to carrier is performed using flip‐chip (C4 ‐ Controlled Collapse Chip Connection) attach. Silicon die size and the quantity of C4 connections for flip‐chip joining have historically been constrained to reduce early life failures caused by solder fatigue wearout. This DNP (distance from neutral point of chip footprint) limitation has been overcome with increasing usage of epoxy encapsulation as a flip‐chip underfill. The encapsulant matches the coefficient of thermal expansion (CTE) of C4 solder and minimises stresses on the interconnection. This enhancement provides a substantial reliability improvement in comparison with unencapsulated packages. Also, it enables larger die with smaller C4 solder bumps on finer pitches to be assembled on ceramic carriers. Recent product development and testing have extended flip‐chip on ceramic packaging technology even further than previously anticipated. Test die up to 20 mm in size with over 2,000 C4 joints have been successfully assembled, encapsulated, stress tested and qualified in CQEP modules. Flip‐chip assembly and encapsulation of C4 connections on very large die to CQFP components have been implemented into IBM manufacturing production. This large‐scale packaging enhancement continues to demonstrate that flip‐chip underfill eliminates the intrinsic failure mechanisms associated with fatigue wearout. This provides a significant technology extension to this low‐cost and high reliability product offering.
Published Version
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