Quad Flat Package Research Articles

A 77 GHz Transmit Array for In-Package Automotive Radar Applications

A packaged transmit array (TA) antenna is designed for automotive radar applications operating at 77 GHz. The compact dimensions of the proposed configuration make it compatible with standard quad flat no-lead package (QFN) technology. The TA placed inside the package cover is used to focus the field radiated by a feed placed in the same package. The unit cell of the array is composed of two pairs of stacked patches separated by a central ground plane. A planar patch antenna surrounded by a mushroom-type EBG (Electromagnetic Band Gap) structure is used as the primary feed. An analytical approach is employed to evaluate the primary parameters of the suggested TA, including its directivity, gain and spillover efficiency. The final design has been refined using comprehensive full-wave simulations. The simulated gain is 14.2 dBi at 77 GHz, with a half-power beamwidth of 22°. This proposed setup is a strong contender for highly integrated mid-gain applications in the automotive sector.

Effects of Thermal-Moisture Coupled Field on Delamination Behavior of Electronic Packaging

Abstract Delamination failure is one of the most prevalent and serious reliability issues in micro-electronic packaging. To understand this phenomenon further, this study constructs an experimental test system consisting of a double cantilever beam (DCB) fixture, an MTS-Acumen microforce tester, and a temperature and humidity controller. The system is employed to investigate the effects of coupled moisture-thermal loading on the critical strain energy release rate (SERR) at the epoxy molding compound (EMC)/Cu leadframe (LF) interface of a very thin quad flat no-lead package (WQFN) assembly. A three-dimensional computational model with hygro-thermal loading conditions is developed to evaluate the moisture diffusion, thermal stress, and integrated stress of a multichip WQFN package under typical processing conditions and precondition tests. The validated simulation model is then applied with the virtual crack closure technique (VCCT) to investigate the fracture behavior at the EMC/Cu LF interface in the WQFN package. The effects of three design parameters on the SERR performance of the package are identified through a parametric analysis. Finally, a Genetic Algorithm (GA) optimization method is employed to examine the effects of the main structural design parameters of the WQFN package on its delamination reliability. The results are used to determine the optimal packaging design that minimizes the SERR and hence enhances the package reliability.

Freeze Frame Reflow to Enhance Yields for Advanced Low-Profile Bottom Terminated Packages

Today, designers are demanding an overall form-factor reduction to save board space, increase functionality, and allocate more circuit board real estate toward end-user applications – all with less space allocated to power management where not just the X-Y shrink but the 3D volumetric shrink is required. Unlike most gull wing style leaded packages, QFNs (Quad Flat Pack No lead packages) also known as BTCs (Bottom Terminated Components) have coplanar terminals below the package body to answer this ever-decreasing form-factor requirement. The final standoff in these QFN style packages are dictated by the solder joint geometry formed. Within this advanced package family also finding a similar trend are power WCSPs (Wafer Chip Scale Packages) where traditional solder spheres are being replaced with low profile interconnects in expanded and asymmetrical geometries. This paper presents factors that influence advanced low standoff package solderability performance with the use of video microscopy and live in situ X-ray reflow. To reflect the QFN board assemblies that are typically designed a series of layouts were implemented across different coupon test boards. Assembled coupon test board were designed by varying 1) through hole via design, 2) solder mask tenting techniques, 3) periphery and center thermal pad printed solder joint volumes, 4) no-clean and water-soluble solder paste flux chemistry all using SAC 305 alloy and type 4.5 powder size. One case study using live in-situ X-ray system will explain the effects of a QFN land pattern layout incorporating vias in the center thermal pad with solder mask tenting over the via openings located on the back of the PCB. In another configuration vias were removed from the center thermal pad and vacuum reflow performed during the liquidus phase of the solder with an explanation of why some of the voids remained. The first and second order results presented within this paper have practical implications and from their observations a novel process evaluation technique coined as Freeze Frame Reflow (FFR) was developed. In the last case study presented, an advanced mrQFN (multi-row QFN) package is investigated for factors affecting yields. FFR is then implemented resulting in an increase in yield further demonstrating the benefits this new & novel technique can offer.

Modeling the Effects of Thermal Pad Voiding on Quad Flatpack No-lead (QFN) Components

Finite element modeling was used to evaluate the effects of thermal pad solder voiding on the thermal resistance of Quad Flatpack No Lead components. This included two different approaches for modeling solder voids: many small, distributed voids, the effects of which were averaged across the entire solder contact area or a single discrete void. Two approaches were used for defining the thermal path established in the solder. The effects of other design parameters - thermal boundary conditions, the presence of thermal vias under the package, and the size of the die power dissipation area – were also addressed. Modeling showed that thermal vias and external boundary conditions had the most significant impact on the package thermal resistance. Solder pad voids and concentrated die-level heat dissipation, for the range used in this study, had noticeable but less significant impacts on thermal resistance. The study also compared different approaches for simulating solder voiding and identified ranges in which modeling simulations are most appropriate.

A Fine Technique for Automatic Inspection of Surface Mount Components

In this paper, a machine vision technology is used to inspect surface mount components (SMC). It can receive the purpose of improving manufacturing losses caused by misjudgments of manual inspection. The detection includes missing parts, wrong parts, skew, reverse polarity, missing pin, bridging, broken pin, etc. The surface mount components to be tested in this paper include QFP (Quad Flat Package) and SOP (Small Outline Package). The proposed method consists of four parts: (1) image capture: capture the printed circuit board (PCB) image in XY-Table through camera; (2) detection: use correlation coefficient to detect missing and wrong parts; (3) positioning: judge from the RGB histogram of the shifting element; (4) segmentation: detect disconnection and bridging defects according to the segmentation result of the cumulative projection.

Effect of the reflow process on IMC growth for different devices and complex components

Intermetallic compound (IMC), as an inevitable part between pad and solder, has a severe effect on the strength and reliability of microelectronic interconnection. Here, an investigation was carried out on IMC growth for different devices and complex components. The device-level experiments were conducted with five factors: peak temperature, time duration above solder liquidus temperature, the thickness of solder paste, surface finish types, and package types including ball grid array (BGA) and quad flat package (QFP). Meanwhile, four complex components with the same reflow profile were conducted and compared for component-level experiments. A scanning electron microscopy (SEM) was used to measure the thickness and determine the spatial distribution of the elements through the IMC. The multivariate analysis of the formation and growth of IMC during reflow soldering was studied based on Nernst–Shchukarev’s equation and the results of the experiments. The difference in IMC thickness between BGA and QFP with different factors was discussed and compared separately. The results showed that the peak temperature and time above liquidus played a vital role in the IMC growth and the solder paste thickness and different pad metallization could not be ignored. SEM pictures of the solder and statistical results were revealed that the surface finish type has a marked impact on the formation of the IMC. For printed circuit board (PCB) with numbers of components, the IMC thickness and uniformity of solder joints at corner and center positions showed some regularity differences. Meanwhile, the bump shape (Cu1−x Ni x )6Sn5 IMC was observed for small size BGA with electroless nickel and immersion gold during the reflow process. The results have a significant meaning to optimize its reflow process parameters for complex components, to improve the interconnection reliability in engineering.

A Parametric Study of Thermal Stress and Analysis of Creep Strain Under Thermal Cyclic Loading in a Hybrid Quad Flat Package

Due to the variation of temperature during service, the leads in quad flat packages (QFP) and plastic leaded chip carrier (PLCC) undergo high thermal stress, which can lead to large deformation and failure. Thus, the prediction of thermal stress and strain distributions is a prerequisite for reliability analysis of such components. Along this line, this work analyzed the performances for gull wing and J-lead with different geometries. The thermal stress and strain distributions of both leads were determined by using the finite-element method (FEM). For each type of the lead, a parametric study was conducted in order to evaluate the effect of lead geometry on stress and strain distributions. Based on the simulation results, an optimum lead design was suggested. In addition, simulation work of package under thermal cyclic loading has been done, accumulated creep strain was found in the critical location of solder in package, and lifetime was predicted.

Performance of a hybrid fine pitch quad flat package mounted with a new flux on printed circuit board in surface insulation resistance test

AbstractAn innovative hybrid quad flat package is designed recently by incorporating two types of leads with two distinctive shapes: gull wing and J‐lead. These leads are separated into two layers to increase the adjacent space between them. Pure tin is used as the connector finish in the package, while Sn‐3.0 Ag‐0.5Cu solder material with a new flux is printed on the footprint copper pads of printed circuit board to join the hybrid packages on it. As compared to the conventional quad flat package, the design significantly increases the lead count by 50 % and reduces the distance between two types of leads to 0.325 mm, consequently improving the functional capability in a smaller size product. Surface insulation resistance test is conducted according to IPC‐TM‐650 standard to analyse the reliability of the newly designed hybrid quad flat package. The absence of tin whisker and dendrite after the test demonstrates the reliability of this hybrid package product and the new flux applied.

Specialized Lead Design of Leadframe Packages for Improved Mold Adhesion

This paper presents an advanced design of Quad-Flat No-leads (QFN) and Quad-Flat Package (QFP) leadframe to mitigate the propagation of delamination between high stress level areas particularly the mold-to-leads interface. The integration of through-hole mechanism on leadframe provides mechanical anchoring of mold material to the lead junction interface and/or vice versa. To produce interlocking, the through-hole design will be penetrated by the epoxy mold compound during conventional molding process affixing each individual lead to the encapsulation material. On the other hand, the package design is materialized through repeated cycle of chemical etching and masking process during leadframe manufacturing, the mechanical anchoring can be implemented on the conventional design of carriers. This approach, considering the design and assembly method of the new leadframe design, is a cost-effective alternative in improving the interfaces of key material such as mold and leadframe.

Modeling and experimental investigation of damage initiation and propagation of LQFP package under thermal cycle

Thermo mechanical fatigue and damage have been always an issue for solder joint materials used in microelectronics. Accurate damage and crack prediction is important to define the life cycle of these joints. This paper provides a finite element modeling approach used in combination with continuum damage model in order to determine damage level, update material’s constituent properties and to predict the damage initiation, damage propagation and time in Low Profile Quad Flat Package solder joint. The successive initiation and propagation of a crack is calculated by a non-linear visco-plastic finite element model. Based on the amount of damage they incur in each stage, their constitutive properties are upgraded. Mesh elements with successive damage are suppressed from the structure. The results of finite elements analysis show that they are softened and can therefore stand more stress as the elements accumulate damage leading to the decrease of damage accumulation level. The initiation site and propagation path were showed very accurately and were confirmed experimentally with scanning electron microscopy.

Modeling and experimentation of creep-fatigue and failure of low-profile quad flat package under thermal cycle

An experimental investigation and numerical modeling using multiphysics finite element method were performed to study the thermal failure mechanism of low-profile quad flat package solder joints of memory module due to low-cycle fatigue. The strain, stress, and number of cycles to failure have been calculated according to a strain life Coffin–Manson and energy-based Morrow fatigue models. Scanning electron microscopy imaging at the end of thermal cycle was used to evaluate the damage initiation and propagation. The effect of the solder volume on fatigue life of solder joints was discussed. Through analyses of theoretical results and experimental data on fatigue life, cracks initiation and propagation have been highlighted and their possible causes have been discussed.

The degradation study for QFP interconnection structure based on PCMD health index and Darveaux model

In electronic assemblies, quad flat package (QFP) is a widely used packaging method and its interconnection structure degradation is an important field in electronic reliability research. Although degradation processes and failure modes of QFP are various, presently, there are few researching articles on the degradation regularity and mechanism under the same failure mode. In this paper, QFP degradation experiment has been carried out. Three typical QFP degradation processes and failure modes are obtained by experiment data and crack microscopic analysis. Degradation features and curves are extracted through the health index from fusion of dynamic principal component and Mahalanobis distance(PCMD). The regularity shows that there is a similar inflection point in degradation rate curves, and degradation rates are significantly different after this point. Then, according to Darveaux failure physical model, the strain energy distribution of the crack initiation and propagation area is obtained by finite element simulation. Results show that average strain energy density in crack initiation area is similar but in crack propagation area is not, resulting in crack initiation at similar time but the crack propagation rate is different.

Influence of Carbon Nanotube Concentration on the Interconnection Properties of Solderable Isotropic and Anisotropic Conductive Adhesive

In this paper, two types of multi-walled carbon nanotube (MWCNT)-filled solderable electrically conductive adhesive (SECA) systems were formulated, a solderable isotropic conductive adhesive (SICA) containing 40 vol% of low melting point alloy (LMPA), and a solderable anisotropic conductive adhesive (SACA) with 20 vol% of LMPA, with different MWCNT contents (0, 0.03, 0.5 and 2 wt%). A quad flat package (QFP) interconnection test was conducted for each SECA system to investigate the influence of the MWCNT concentration on the interconnection properties of the SICA and SACA systems. The results indicated that the interconnection properties (i.e., electrical and mechanical properties) of each SECA were enhanced at low MWCNT concentration, due to the reinforcing effects of the MWCNT. However, the interconnection properties of each SECA joint deteriorated with increasing MWCNT concentration over 0.5 wt% because of defects in the conduction path, such as entrapped MWCNT-filled polymer (SICA), or reduction of the conduction path area (SACA) due to increased polymer viscosity and diminished molten LMPA mobility. Key words: Anisotropic conductive adhesive, Defect, Interconnection properties, Isotropic conductive adhesive, Low melting point alloy, Multi-walled carbon nanotube

Study on Establishing Degradation Model of Chip Solder Joint Material under Coupled Stress.

The chip is the core component of the integrated circuit. Degradation and failure of chip solder joints can directly lead to function loss of the integrated circuit. In order to establish the degradation model of chip solder joints under coupled stress, this paper takes quad flat package (QFP) chip solder joints as the study object. First, solder joint degradation data and failure samples were obtained through fatigue tests under coupled stress. Three types of micro failure modes of solder joints were obtained by scanning electron microscope (SEM) analysis and finite element model (FEM) simulation results. Second, the characterization of degradation data was obtained by the principal component of Mahalanobis distance (PCMD) algorithm. It is found that solder joint degradation is divided into three stages: strain accumulation stage, crack propagation stage, and failure stage. Later, Coffin–Manson model and Paris model were modified based on the PCMD health index and strain simulation. The function relationship between strain accumulation time, crack propagation time, and strain was determined, respectively. Solder joint degradation models at different degradation stage were established. Finally, through strain simulation, the models can predict the strain accumulation time and failure time effectively under each failure mode, and their prediction accuracy is above 85%.

Defect minimization and process improvement in SMT lead-free solder paste printing: a comparative study

PurposeThe purpose of this paper is to investigate and minimize the printing-related defects in the surface mount assembly (SMA) process.Design/methodology/approachThis paper uses an experimental approach to explore process parameter and printing defects during the SMA process. Increasing printing performance, various practices of solder paste (Ag3.0/Cu0.5/Sn) storage and handling are suggested. Lopsided paste problem is studied by varying squeegee pressure and the results are presented. Unfilled pads problems are observed for ball grid array (BGA) and quad flat package (QFP) which is mitigated by proper force tuning. In this paper, a comparative study is conducted which evaluates the manifestation of printing offset due to low-grade stencil. The input/output (I/O) boards were oxidized when the relative humidity was maintained beyond 70 per cent for more than 8 h. This pad oxidation problem is overcome by proper printed circuit board (PCB) handling procedures. When the unoptimized line is used, the paste wedged in the stencil and influences the performance of the screen printer, for this reason, an optimized line is proposed that minimize the printing defects.FindingsThe key findings are as follows: in the SMA process, printing quality is directly associated with solder paste quality. Experimentally, it is observed that a considerable variance in solder deposition occurred when the front and rear squeegee have different configurations. High-grade and unsoiled stencil results in superior paste deposition and less distinction. Insufficient solder paste and bridge problems also occur in printing when PCB pads are oxidized. Optimized line resolves solder paste clog issues, associated with stencil’s aperture. The cooling arrangement on the conveyor, after reflow, explicates hot jig problem. Control environmental conditions minimized static charges and printing defects.Originality/valueThe preceding studies emphasis mostly on the squeegee pressure, while other important parameters are not completely investigated. Moreover, it is very imperative to concurrently measure all parameters while varying the environmental conditions. This study highlights and provides an experimental approach to various PCB printing defects, and a comparative study has been conducted that concurrently measure all process parameters.

Dust and Water Resistance Testing Methodology for Environmental Sensors

Abstract This paper explores the “IEC standard 60529 International Protection Marking” also sometimes referenced as Ingress Protection Marking and how it applies to mobile and wearable electronics on a component level. The testing methodology used for an OCQFN (Open Cavity Quad Flatpack No-lead) humidity sensor will be evaluated including pass/fail criteria. The applicability of this standard has been developed to verify the robustness of finished mechanical assemblies intended to be put in static mounted applications but in this case has been adopted to verify the robustness of a semiconductor based sensor at a packaging level with accelerated pre-conditioning to predict the end of life performance.

Quad Flat Package with Embedded ESD Diode on Leads

Quad Flat Package with Embedded ESD Diode on Leads

Effect of Air-HAST Conditions on Sn Whisker Growth

Sn whiskers are one of the major causes of failure in fine-pitch electronics because of the short distance between the leads in an electronic package. In various whisker mechanisms, it takes a long time to grow a whisker due to Sn corrosion because the temperature is limited to below 100°C in high humidity. In the highly accelerated temperature and humidity stress test (HAST), the corrosion phenomenon rarely occurred because of the little air inside the chamber. Therefore, air is needed in the whisker accelerating test to meet the same whisker mechanism under high temperature and humidity conditions. In this study, an Air-HAST with air inputs in the chamber with highly temperature and humidity was introduced. Whisker growth was accelerated with temperatures at 130°C and various air pressures using the thin quad flat package (TQFP) sample with Sn plating lead. The whisker growth in the Air-HAST, HAST, and high temperature and high humidity test (85°C, 85%R.H.) was compared by plotting each growth length and number of whiskers. The accelerated relationships of whisker growth under the various test conditions will help the electronic industry meet the short development cycles. Key words: Sn whisker, Air-HAST, 85°C/85%RH, HAST, TQFP

TRAC: A Thermal Resistance Advanced Calculator for Electronic Packages

This paper presents a novel simulation tool named thermal resistance advanced calculator (TRAC). Such a tool allows the straightforward definition of a parametric detailed thermal model of electronic packages with Manhattan geometry, in which the key geometrical details and thermal properties can vary in a chosen set. Additionally, it can apply a novel model-order reduction-based approach for the automatic and fast extraction of a parametric compact thermal model of such packages. Furthermore, it is suited to automatically determine the joint electron device engineering council (JEDEC) thermal metrics for any choice of parameters in a negligible amount of time. The tool was validated through the analysis of two families of quad flat packages.

Influence of Interfacial Intermetallic Growth on the Mechanical Properties of Sn-37Pb Solder Joints under Extreme Temperature Thermal Shock

Solder joints in thermally uncontrolled microelectronic assemblies have to be exposed to extreme temperature environments during deep space exploration. In this study, extreme temperature thermal shock test from −196 °C to 150 °C was performed on quad flat package (QFP) assembled with Sn-37Pb solder joints to investigate the evolution and growth behavior of interfacial intermetallic compounds (IMCs) and their effect on the pull strength and fracture behavior of Sn-37Pb solder joints under extreme temperature environment. Both the scallop-type (Cu, Ni)6Sn5 IMCs at the Cu lead side and the needle-type (Ni, Cu)3Sn4 IMCs at the Ni-P layer side changed to plane-type IMCs during extreme temperature thermal shock. A thin layer of Cu3Sn IMCs was formed between the Cu lead and (Cu, Ni)6Sn5 IMC layer after 150 cycles. The growth of the interfacial IMCs at the lead side and the Ni-P layer side was dominated by bulk diffusion and grain-boundary diffusion, respectively. The pull strength was reduced about 31.54% after 300 cycles. With increasing thermal shock cycles, the fracture mechanism changed from ductile fracture to mixed ductile–brittle fracture, which can be attributed to the thickening of the interfacial IMCs, and the stress concentration near the interface caused by interfacial IMC growth.