Abstract
This paper presents a novel simulation tool named thermal resistance advanced calculator (TRAC). Such a tool allows the straightforward definition of a parametric detailed thermal model of electronic packages with Manhattan geometry, in which the key geometrical details and thermal properties can vary in a chosen set. Additionally, it can apply a novel model-order reduction-based approach for the automatic and fast extraction of a parametric compact thermal model of such packages. Furthermore, it is suited to automatically determine the joint electron device engineering council (JEDEC) thermal metrics for any choice of parameters in a negligible amount of time. The tool was validated through the analysis of two families of quad flat packages.
Highlights
In the last two decades many efforts have been made to improve the way semiconductor vendors deliver thermal data of electronic components to their customers
thermal resistance advanced calculator (TRAC) is suited to automatically compute the joint electron device engineering council (JEDEC) metrics θJA, ΨJB, ΨJCtop, θJB, θJCtop, θJCbottom [2] in 4 ambients, which differ in terms of thermal path followed by the heat generated within the heat sources (HSs) to emerge from the die; : the ambient to evaluate θJCbottom requires a cold plate in intimate contact with the package backside; for the computation of θJCtop the plate is located over the top surface; in the ambient for determining θJB, a cold ring surrounds the package; no cooling systems are exploited in the ambient common to θJA, ΨJB, ΨJCtop
As far as the boundary conditions (BCs) are concerned, specific values of heat transfer coefficients are applied to all surfaces of any structure under test for each ambient; such values were preliminarily calibrated by comparing the JEDEC metrics simulated with commercial numerical programs with the experimental counterparts for a broad variety of package families
Summary
In the last two decades many efforts have been made to improve the way semiconductor vendors deliver thermal data of electronic components to their customers. For the specific case of parametric CTMs (pCTMs) [4], the proposed MOR-based technique starts from the detailed thermal model (DTM) of an electronic component, some parameters of which (geometrical dimensions and thermal properties) are assumed to vary in a chosen set, either finite or infinite It fully automatically extracts a BCI pCTM, which depends on the assigned set of parameters and ensures a selected level of accuracy. It is suited to automatically calculate the JEDEC thermal metrics of any product of the assigned family of packages from the above parametric models in a very low (pDTM) or negligible (pCTM) amount of time By virtue of such appealing features, TRAC can be helpful for vendors and customers in the semiconductor industry.
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