Leadless IC package with a substrate produced by copper/nickel/copper-3-layer-clad material

Abstract

Terminal units such as mobile phones, portable game systems and electronic books, have spread all over the world and advanced to be smaller, more lightweight and thinner every moment. Simultaneously, the inner electronic parts such as batteries, IC packages and connectors were also smaller and thinner. For example, in order to reduce the occupied area and space on the printed circuit board (PCB), some lead flame type IC packages such as SOP(Small Outline Package) and QFP(Quad Flat Package) have changed to leadless type ones such as SON(Small Outline Non-lead), QFN(Quad Flat Non-lead) and LGA. (Land Grid Array) The substrates of such leadless IC packages are usually made of a single metal plate such as a copper, a copper alloy and a nickel and conventionally produced through etching process or plating process. So the designs for the package like the size, the number of terminal and the total thickness are limited. In order to solve such problems, we developed a new manufacturing method, using clad materials which rolled copper (Cu) foil and nickel (Ni) plating layer on electrolysis Cu foil were laminated. In detail, the components were consisting of 18μm to 35μm thickness Cu foil with about 1 um thickness Ni plating layer and around 100μm thickness rolled Cu sheet (Cu/Ni/Cu material). These materials are characterized by the cladding interface between the rolled Cu foil and the Ni plating layer on the electrolysis Cu foil, which is bonded by the surface activated bonding (SAB) method [1, 2, 3]. Namely, the interface is so flat that it is suitable to use for selective etching work [4, 5]. In this paper, we would like to introduce the new IC package manufacturing process with the Cu/Ni/Cu material. This method makes some new package designs possible and achieves high productivity when comparing to the conventional method. We produced various leadless IC packages with the total thickness of 0.25mm to 0.5mm, with the number of 3 to 460 terminals at 1 row to 4 rows for terminals by means of this new method. In addition, in order to evaluate the package performance, we made the package with the total thickness of 0.43mm, with 164 terminals of diameter of 0.25mm at 3 rows and the terminal pitch of 0.5mm. In this sample, heat-tolerance by the solder reflow test with the pre-condition of JEDEC (Joint Electron Device Engineering Council) standard of level 3 was estimated and the package warpage in the range of 25 to 260 degrees Celsius was measured. As the results, the package sample could pass the reflow test of the JEDEC level 3 and the warp of the package was less than 50μm.