PWM Strategy Research Articles

Low Frequency Harmonics Reduction Discontinuous PWM Strategy With Active Neutral Point Voltage Control for Neutral Point Clamped Three-Level Inverter

The traditional discontinuous pulse width modulation (DPWM) strategy is very suitable for reducing the switching losses of three-level inverter (TLI). However, large neutral point voltage (NPV) fluctuation is usually caused, which results in low frequency harmonics (LFHs) in the output line voltage. Therefore, a DPWM modulation strategy that can suppress LFHs is presented in this paper, and it is recorded as low frequency harmonic reduction DPWM (LFHRDPWM). The proposed LFHRDPWM can be seen as an improvement of traditional DPWM, which modifies the duty ratios according to voltages of the two DC-link capacitors. For LFHRDPWM, due to the suppressed LFHs, the self-balancing ability of NPV is thus lost, and gradually increased DC offset on NPV is caused. To overcome that, an active neutral point voltage control (ANPVC) method is also proposed. The proposed methods not only can achieve switching loss (SL) reduction almost as the same as traditional DPWM strategy, but also can realize NPV control and LFHs reduction. The effectiveness of the proposed method is verified by experiments.

DC-Link Quasi-Switched Boost Inverter With Improved PWM Strategy and its Comparative Evaluation

Low voltage stress on the impedance source network devices is the main reason for the advent of DC-linked type quasi-switched boost inverters (DqSBIs). However, the DqSBI has become less attractive due to its low voltage gain. This paper presents a novel PWM control strategy for the DqSBI and its comparative performance evaluation to the conventional inverters. The modified PWM control strategy based DqSBI improves the voltage gain and reduces the conduction loss and the inductor current ripple. Circuit analysis and comparison study between the DqSBI, the quasi-Z-source inverters, and the two-stage inverter with a boost DC-DC converter are presented. 1-kVA three-phase inverter prototypes were set up to compare and evaluate the performance of the DqSBI with the improved PWM method for voltage gains of 0.85 to 1.6. The measured efficiency and total harmonic distortion (THD) values are also presented.

Control Strategy for a Five-Leg Inverter Supplying Dual Three-Phase PMSM

This study presents a novel control strategy for a five-leg inverter-fed dual three-phase permanent-magnet synchronous motor (DT-PMSM)system. Three different five-leg inverter topologies (operating modes) can be reconfigured by choosing a pair of phases for sharing the common leg. The five-leg inverter operation mode with 150° phase difference can achieve full torque output, but the utilization of DC bus voltage is low. The operation mode with 30° phase difference has higher DC bus voltage utilization but lower output torque. The modified double zero-sequence injection (DZI) PWM strategy based on carrier-based PWM (CBPWM) for five-leg inverter operating modes is proposed. This strategy can achieve the maximum DC bus voltage utilization. The five-leg inverter operating modes can be used as a fault-tolerant solution for the occurrence of a fault in one leg of the six-leg inverter. Compared with the commonly used open phases fault-tolerant control (FTC) strategies, this strategy has the advantages of without increasing the stator copper, reducing the torque ripples, and implementing easily. Experimental results verify the effectiveness and feasibility of the proposed strategy.

An Efficient Digital Space Vector PWM Module for 3-φ Voltage Source Inverter (VSI) on FPGA

The realization of digital control circuitry based PWM strategies provides many advantages. It includes better prototyping, higher switching frequency, simple hardware, and flexibility by overcoming the limitations of analog control strategies. In this article, The Digital space vector-based Pulse width Modulation ((DSV-PWM) is designed. The DSV-PWM Module includes, mainly, Xdq reference frame, Sector generation, Square root, switching time generation, Carry-save adder (CSA), and PWM Generation module. These modules are designed using simple logical operations, and combinational circuits to improve the DSV-PWM performance. The DSV-PWM Module is synthesized and implemented on a cost-effective Artix-7 FPGA device. The present work utilizes a < 1% chip area, operates at 597.83 MHz of maximum frequency, and utilizes 110mW of total power on FPGA Device. The DSV-PWM module is also compared with the existing SV-PWM approach with better improvement in hardware constraints like chip area, operating frequency, and dynamic power (mW).

Custom Power Device in Multilevel Inverter for Power Quality Improvement

A dynamic voltage restorer (DVR) is a FACTS gadget, which is utilized fundamentally in transmission lines to remunerate the voltage list and voltage swell that happens on hold. A DVR is a circuit, which made out of intensity electronic parts like diodes and thyristors. It is generally utilized because of its miniature size and proficient activity. This paper proposes a cascaded inverter type DVR to repay voltage hang in the utilities for power appropriation, which is used for country zone advancement. The DVR infuses a voltage arrangement to the framework voltage. The multi carrier PWM strategy is utilized to produce terminating voltage to inverter. The proposed framework decreases the voltage list and complete consonant bending of the conveyance framework. The proposed framework is simulated utilizing the MATLAB/Simulink.

Line Current Ripple Minimization PWM Strategy With Reduced Zero-Sequence Circulating Current for Two Parallel Interleaved Three-Phase Converters

This article proposes a line-current ripple minimization pulsewidth modulation strategy with reduced zero-sequence circulating current (ZSCC) for two parallel three-phase two-level converters. We split each 60° sector into six subsectors, each applies the nearest three vectors to ensure minimal line-current ripple. To reduce the ZSCC, we further investigate all vector sequences of the nearest three vectors and derive an optimal vector sequence for each of the six subsectors. We unify all carrier sequences under a carrier-based modulation scheme with the assistance of voltage injections. The injected voltage can be computed by a simple algorithm that allows easy implementation in mainstream microcontrollers. The experimental results validate that the proposed method maintains the minimal line-current ripple while significantly reducing the ZSCC compared to the existing line current ripple minimization methods.

Experimental study of PWM strategy effect on acoustic noise generated by inverter‐fed induction machine

Experimental study of PWM strategy effect on acoustic noise generated by inverter‐fed induction machine

Optimum pulse-width modulation strategy for a symmetric cascaded multilevel inverter

This paper investigates for the most suitable PWM strategy for a symmetric cascaded multilevel inverter. The objective is to determine a PWM switching strategy which optimises inverter performance by ensuring higher DC link utilisation and minimum total harmonic distortion (THD) at low switching frequency to minimise switching power losses. Simulations carried out in MATLAB-Simulink environment has given an insight of inverter performance when carrier-based PWM techniques are applied. In this parametric evaluation, both odd and even multiples of 50 Hz modulating signal were applied for obtaining switching frequency for various multicarrier-based PWM strategies.

Controlling Devices by IoT

Internet of Things (IoT) is an emerging technology not only is being used in computer applications but also in controlling electronic devices. In this paper IoT is being employed to control a single-phase induction motor. By implementing this technique and using a wireless speed controller a single-phase induction can be controlled from any location across the world. Demonstration setup included a single-phase induction motor of 230 volts and 50 Hertz is interfaced with the microcontroller (PIC16F877A). Interfacing is done through opto coupler (MOC3021) and triac (BT136) and Speed for various PWM scheme was determined.

Improved Synchronized Space Vector PWM Strategy for Three-Level Inverter at Low Modulation Index

Aimed at reducing the switching loss and common-mode voltage amplitude of high-power medium-voltage three-level inverter under low modulation index conditions, an improved synchronous space vector PWM strategy is proposed in this paper. The switching times in each fundamental period are reduced by the re-division of small regions and the full use of the redundant switching state. The sum of switching algebra is introduced as an evaluation index and the switching state with the minimum value of the sum of switching algebra are adopted. Then, the common mode voltage amplitude is reduced. The theoretical analysis and experimental results show that the improved modulation strategy proposed in this paper can effectively reduce the switching loss and common-mode voltage amplitude of the inverter under the condition of the low modulation index. Moreover, the neutral-point voltage ripple is also reduced simultaneously.

Common-Mode Current Reduction with Synchronized PWM Strategy in Two-Inverter Air-Conditioning Systems

Common-Mode Current Reduction with Synchronized PWM Strategy in Two-Inverter Air-Conditioning Systems

Fault‐tolerant compensation control for T‐type three‐level inverter with zero‐sequence voltage injection

This study proposes a carrier-based PWM strategy with zero-sequence voltage injection for T-type three-level inverter to a tolerant open-circuit fault. The half-bridge and NP bridge open-circuit faults are analysed. The faulty switch can be identified by the average phase current and the deviation of neutral-point (NP) voltage. In the case of half-bridge failure, the fault-tolerant control reduces the distortion of phase current and the amplitude of line-to-line voltage is decreased. In the case of NP failure, the faulty pole voltage becomes two-level instead of three-level and the phase voltage is not reduced. By using the novel zero-sequence voltage injection, the NP voltage is balanced in both half-bridge and NP bridge failures, which do not require additional hardware and complex calculations. The effectiveness of the proposed fault-tolerant PWM strategy and injection of zero-sequence voltage is validated by the simulation and experiment results.

Uniform Distribution Pulsewidth Modulation Strategy for Three-Phase Converters to Reduce Conducted EMI and Switching Loss

It is necessary to suppress the emission level of conducted electromagnetic interference (EMI) for the power electronics converters, and the variable switching frequency pulsewidth modulation (VSFPWM) is an alternative approach to reduce conducted EMI without adding bulky passive components. However, the experimental results indicate that many obvious EMI spikes in spectrum remain so that the conducted EMI reduction for VSFPWM is limited. In order to eliminate the EMI spikes in spectrum, this article first investigates the cause of the EMI spikes for VSFPWM, and the analysis results show that the nonuniform distribution of switching frequency is the primary reason. Then, a novel PWM strategy called uniform distribution PWM (UDPWM) is proposed to eliminate the EMI spikes and to further reduce conducted EMI. The design of a UDPWM is based on the uniform distribution of switching frequency and the principle of less switching loss. Moreover, the analytical formula of switching frequency is also deduced in detail, which adopts fixed variation range of switching frequency whatever the modulation index is. Finally, the experiments are carried out to validate the effectiveness of the UDPWM in reducing conducted EMI and switching loss. The UDPWM can approximately reduce conducted EMI by 20 dB compared with the conventional constant switching frequency PWM, and all obvious spikes in the spectrum are eliminated compared with VSFPWM.

Improvement of power utilisation capability for a three‐phase seven‐level CHB inverter using an improved selective harmonic elimination–PWM scheme by sharing a desired proportion of power among the H‐bridge cells

An improved selective harmonic elimination-pulse width modulation (SHE-PWM) scheme has been proposed for a three-phase seven-level cascaded H-bridge (CHB) inverter that enhances the power utilisation capability of the inverter by sharing the desired amount of power among the H-bridge cells and also eliminates both 5th- and 7th-order harmonic components from the inverter output voltage maintaining the desired fundamental voltage component for a wide range of modulation index. Compared to conventional SHE-PWM, this scheme introduces two additional switching in the first cell, while the second and the third cells are switched at advanced switching angles. The differential search algorithm (DSA) technique has been applied to solve the proposed SHE-PWM scheme, and it exhibited comparatively better performance than the algorithm based on genetic algorithm, BEE algorithm and particle swarm optimisation. The effectiveness of the proposed scheme has been verified by both simulation and experimental study on a seven-level CHB inverter. Finally, the proposed scheme has been applied to the closed-loop constant V/f control of the induction motor drive application. It has been established that the proposed scheme is independent of the load power factor angle, and it improved the power conversion efficiency of the conventional SHE-PWM scheme.

Alternating Submodule Configuration Based MMCs With Carrier-Phase-Shift Modulation in HVdc Systems for DC-Fault Ride-Through Capability

DC short-circuit fault ride through is one of the most important characteristics for the modular-multilevel converters (MMC) employed in high-voltage direct-current (HVdc) transmission systems. During the faults, for providing a fault-tolerant control with reactive power compensation to the grid, the MMC normally changes its structure, which requires a remarkable modification and burden computation for implementing the modulation technique in the MMC. This paper proposes an alternative submodule configuration of the MMC based on a carrier-phase-shift PWM scheme, which is easily implemented for switching the operation modes of the MMC from normal condition to fault-tolerant control. The arms of the proposed MMC are configured by typical half-bridge submodules (HBSM) and suggested series-connected triple SMs (SCTSM) in interleaving series, where the SCTSM is composed of three HBSMs connected in series through an additional IGBT and a clamp diode. With the additional IGBTs and diodes, the SCTSMs can produce bipolar output voltages and the MMC can be restructured to operate as three-phase cascaded multilevel converter during pole-to-pole short circuits to control the converter currents. In addition, the cost and power loss of the proposed MMC are lower than those of the existing MMCs based on full-bridge SMs (FBSM), a hybrid of HBSMs and FBSMs, and clamp-double SMs. PSIM simulation results for the 300 MW-300 kV HVdc system with the proposed MMCs are shown to verify the effectiveness of the scheme.

Experimental Verification of Three phase quasi Switched Boost Inverter with an Improved PWM Control

&lt;p&gt;In this paper, an experimental investigation of a three phase quasi Switched Boost Inverter (qSBI) topology is proposed and analysed with an improved Pulse Width Modulation strategy. The qSBI is capable of providing both boost and inversion actions in a single stage. The improved PWM control technique can provide a higher boost with the reduced duty ratio. The theoretical analysis presented in this work is validated using an experimental set up of 100W qSBI topology and hardware results are shown for verification. The improved PWM strategy is implemented and firing pulses are generated in FPGA SPARTAN 3E kit. With the duty ratio of 0.05, the peak ac load voltage of 80 V is obtained. The performance of three phase qSBI is analysed with both conventional PWM strategy and improved PWM strategy. The observations are presentated in detail.&lt;/p&gt;

A novel impedance source fed H-type flying capacitor multilevel inverter

&lt;p&gt;In this paper, simulation using MATLAB/SIMULINK is performed with&lt;br /&gt;bipolar triangular fixed amplitude multi-carrier Phase Disposition (PD)&lt;br /&gt;PWM strategy with sine wave, Third Harmonic Injection, 60 degree Pulse Width Modulation and stepped wave reference for the chosen impedance Source based H-Type flying capacitor Multilevel Inverter (ISBH-Type FCMLI). The root means square value of the fundamental component and Total Harmonic Distortion of the output voltage which are the most important performance indices for the chosen inverter topologies are evaluated presented and compared for various references through duty ratios. From the simulation results it is observed that for various references the THD is almost similar but the root mean square value in terms of voltage is more for THI, 60 degree PWM and stepped wave reference with phase disposition strategy. The results are obtained for ma (amplitude modulation index) &amp;lt; 1 (under amplitude modulation index), ma=1 (normal amplitude modulation index) and ma &amp;gt; 1 (over amplitude modulation index).&lt;/p&gt;

A Novel Discontinuous PWM Strategy to Control Neutral Point Voltage for Neutral Point Clamped Three-Level Inverter With Improved PWM Sequence

In order to reduce switching loss of neutral point clamped three-level inverter (NPC TLI), generally discontinuous pulsewidth modulation (DPWM) is used. But it can result in dc offset and ac ripple on neutral point (NP) voltage. So a novel pulse sequence DPWM (NPSDPWM) is proposed to reduce switching loss and control NP voltage simultaneously in this paper. NP voltage is controlled by choosing proper clamping modes. To avoid unexpected switching action during changing clamping mode, an improved pulse sequence is also presented. The switching loss and NP voltage ripple of NPSDPWM, traditional and proposed DPWM in previous literature are compared, respectively. The experimental results show that NPSDPWM has well NP voltage control ability and the switching losses are reduced effectively.

Three-Phase Symmetric Cascading Z-Source Seven Levels Multilevel Inverter Excited by Multi Carrier Sinusoidal Pulse Width Modulation Scheme

The Multilevel Z sources Inverter have been documented as attractive topologies used for elevated voltage adaptation. As the digit of levels improved, the synthesized set of steps output waveform have many ladder, imminent the preferred sine waveform but the major weakness of MLI be its amplitude of ac output voltage is imperfect to DC input sources voltage summing up. To conquer this drawback seven level cascading symmetric multilevel inverter based Z source inverter have been projected. This work focuses on different multi-carrier sinusoidal PWM scheme for the seven level three phase Z source symmetric cascading inverter. Performance parameters of seven level three phase Z source symmetric cascading inverter has been analyzed. A simulation circuit model of seven level three phase Z source symmetric cascading inverter urbanized using MATLAB/SIMULINK and its presentation have been urbanized.

A Novel Discontinuous Modulation Strategy With Reduced Common-Mode Voltage and Removed DC Offset on Neutral-Point Voltage for Neutral-Point-Clamped Three-Level Converter

In this paper, a novel discontinuous pulsewidth modulation (DPWM) modulation strategy for a neutral-point-clamped (NPC) three-level converter (TLC) is proposed to reduce the switching loss, reduce common-mode voltage (CMV), and remove dc offset from the neutral-point (NP) voltage simultaneously, which is named as RCMV_DPWM. Based on the space vector diagram with reduced CMV, all clamping modes under RCMV_DPWM are revealed. Then, the NP voltage is controlled by selecting proper clamping mode. The realization of RCMV_DPWM is also discussed. Moreover, the performances of RCMV_DPWM are analyzed and compared with other PWM strategies in term of the NP voltage ripple, switching loss, and waveform quality. Finally, the feasibility and superiority of RCMV_DPWM are verified by experiments.