Punch-through Insulated Gate Bipolar Transistors Research Articles

The Advantages and Applications of IGBT Compared with Conventional BJT and MOSFET

Nowadays, the power semiconductor devices have been used in many fields like wind power generation systems, the rail transit. Bipolar junction transistors (BJTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) as well as some other devices are the dominating the market. The insulated gate bipolar transistor (IGBT) as a mixed device of the BJT and the MOSFET, has a preeminent performance. In this paper, the characteristics of the punch through IGBT (PT-IGBT), the MOSFET and the BJT will be investigated by TCAD. Then the PT-IGBT is compared with the BJT and the MOSFET, for concluding its advantages. According to the simulation result, the PT-IGBT has the on-state current of 9*10-4A and the forward blocking voltage of 1200V, which are much higher than the other two devices. In the end of the paper, the development of the semiconductor devices is predicted, about the research trends.

Analytical Model for the Breakdown Voltage in Punch-through IGBTs

Insulated-gate bipolar-transistors (IGBTs) are becoming the main switching devices in medium- and high-power applications, such as switched-mode power supplies, power switches, variable frequency driver circuits, traction motors, and inducting heating. Although the switching speed of IGBTs is lower than in the case of metal-oxide-semiconductor field-effect-transistors (MOSFETs), the forward voltage drop is significantly lower, particularly in higher blocking voltage rated devices, which provides major advantage for using IGBTs in many applications. In addition, IGBTs have higher breakdown voltage and currant handling capacity than traditional bipolar-junction-transistors (BJTs), which makes them attractive for a variety of applications related to electric power switches. In this presentation, we introduce two new analytical models for the breakdown voltage of the punch-through IGBTs. The models are based on the accurate analytical estimation of the ionization integral and the solution of the Poisson equation in the drift region, which lead to a nonlinear equation for the breakdown voltage as a function of the doping concentrations in the drift region, buffer layer, and gate and emitter junctions, as well as of the widths of these regions and junctions. In general, this equation does not have an analytical solution and needs to be solved numerically in order to compute the breakdown voltage. Analytical solutions can be found only in a number of particular cases that will be discussed at the conference. The numerical and analytical solutions of the breakdown voltages are compared to more accurate results obtained using Synopsys’s Sentaurus Device Simulator [1], which is a commercial-grade finite element semiconductor simulator. We observe a very good agreement between our models and the finite element simulations for a wide range doping concentration and geometric dimensions of the IGBTs. In addition, at the conference, we will also compare our analytical results with previous analytical results published in the literature [2]. The proposed analytical model provides an efficient way to design the geometry and doping concentration profiles in punch-through IGBTs and helps the optimization process of the breakdown voltage in these devices [3]. More details about the approximations used in our analytical calculations, the results of the comparison with the more precise finite element simulations, and the existing literature will be presented at the conference. [1] 2016 Sentaurus Device Simulator User Manual, www.synopsys.com[2] J. Baliga, Fundamentals of Power Semiconductor Devices: Springer, 2008. [3] Zhu, C., & Andrei, P. (2017). Sensitivity of Breakdown Voltage of Power Transistors to Dopant Impurities. ECS Transactions, 80(7), 171-179.

Adjoint method for the optimization of insulated gate bipolar transistors

A mathematical algorithm is presented for the computation of optimum doping profiles that maximize the breakdown voltage and on-state current in insulated gate bipolar transistors (IGBT). The algorithm is based on the evaluation of doping sensitivity functions, which are defined as the functional derivatives of the breakdown voltage and on-state current with respect to doping concentration. These functions are computed using an adjoint method and are used in combination with a gradient-based technique to search the optimization space of possible doping configurations efficiently. The mathematical algorithm is implemented numerically to optimize semiconductor devices that are simulated using finite element models and, then, applied to punch-through IGBTs with planar structure. In order to optimize the breakdown voltage it is shown that it is optimum to decrease the doping concentration in the drift region, particularly near the p-type junction on the emitter side and introduce p-type layers with low doping concentration in the drift region. In the case of the on-state current it is optimum to increase the n-type concentration the drift region, near the emitter junction. Depending on the initial structure and criteria imposed during the optimization, it is possible to increase the breakdown voltage by at least 5-10% and decrease the on-state voltage by at least 200 mV. The algorithm presented in this article can be easily extended to the optimization of three-dimensional doping profiles and to the optimization of other power devices, such that power p-n junctions and power metal-oxide-semiconductor field-effect-transistors.

Optimization of Doping Profiles in Insulated-Gate Bipolar-Transistors Using a Large Scale Optimization Technique

There is much interest on the numerical and practical optimization of the doping profiles in semiconductor devices. This interest is mostly driven by the power semiconductor industry, which is in continuous search for higher breakdown voltage semiconductor switches that have lower on-state resistance, and high current handling capacity and switching speeds. Among the existing power semiconductor devices, insulated-gate bipolar-transistors (IGBTs) are becoming more and more attractive because of their high blocking voltage capabilities and on-state current. Although these devices suffer from a relatively lower switching speed compared to current state-of-the-art metal-oxide-semiconductor field-effect-transistors, IGBTs have already become the preferred switching devices in many power applications, such as induction heating applications, traction motors, etc. [1]. In this work we present numerical finite element optimization results for a realistic 70 mm-wide punch-through IGBT structure. The optimization focusses on the two-dimensional doping distribution of the gate, emitter and collector junctions, and of the drift and buffer layers in order to increase the breakdown voltage of the IGBT. The optimization method is based on an adjoint space technique that our group has recently developed for the design of nanoscale semiconductor devices, and which is adjusted here to compute the doping sensitivity functions of the breakdown voltage and on-state resistance in IGBTs [2-4]. These doping sensitivity functions show how sensitive the breakdown voltage and on-state resistance are when we add one additional acceptor or donor impurity at a particular location inside the semiconductor. Since the doping sensitivity functions provide information about the gradient of the breakdown voltage and on-state resistance with respect to the doping concentration they are instrumental for the numerical and practical optimization of IGBTs. As we will show at the conference, we are able to increase the breakdown voltage from approximately 300 V to over 700 V without deteriorating the on-state resistance of the transistor. In the full presentation we will describe how the adjoint method can be used to calculate the doping sensitivity functions of the breakdown voltage, on-state current and voltage, and on-state resistance. We will also present details about the numerical implementation of the optimization method, which is based on a modified gradient optimization appropriate for semiconductor devices. Note that most traditional optimization approaches such as the steepest descends method, the Broyden–Fletcher–Goldfarb–Shanno algorithm, or similar algorithms fail because of the doping concentration varies over many orders of magnitude, which vary can from region to region inside the same device.

Investigation on Current Crowding Effect in IGBTs

This paper investigates the influences of various topside cell structures of insulated gate bipolar transistor (IGBT) on the current crowding effect during high current turn-OFF by symmetrical multicell numerical simulations. It is observed that lower breakdown electric field in the drift region can reduce the negative differential resistance in the forward blocking curve and therefore suppress the current crowding effect during high current turn-OFF. We refer to this characteristic as the self-suppressing current crowding effect (SSCCE). Different topside cell structures of IGBT have considerable influence on the SSCCE. A modest increment of the SSCCE by proper topside structure design provides an alternative solution to improve the ruggedness of IGBT, especially for the strong punchthrough or low current gain IGBTs.

고전압 Non Punch Through IGBT 및 Field Stop IGBT 최적화 설계에 관한 연구

An IGBT (insulated gate bipolar transistor) device has an excellent current-conducting capability. It has been widely employed as a switching device to use in power supplies, converters, solar inverters, and household appliances or the like, designed to handle high power. The aim with IGBT is to meet the requirements for use in ideal power semiconductor devices with a high breakdown voltage, an on-state voltage drop, a high switching speed, and high reliability for power-device applications. In general, the concentration of the drift region decreases when the breakdown voltage increases, but the on-resistance and other characteristics should be reduced to improve the breakdown voltage and on-state voltage drop characteristics by optimizing the design and structure changes. In this paper, using the T-CAD, we designed the NPT-IGBT (non punch-through IGBT) and FS-IGBT (field stop IGBT) and analyzed the electrical characteristics of those devices. Our analysis of the electrical characteristics showed that the FS-IGBT was superior to the NPT-IGBT in terms of the on-state voltage drop.

Current Sharing Control Strategy for IGBTs Connected in Parallel

This work focuses on current sharing between punch-through insulated gate bipolar transistors (IGBTs) connected in parallel and evaluates the mechanisms that allow overall current balancing. Two different control strategies are presented. These strategies are based on the modification of transistor gate-emitter control voltage V_GE by using an active gate driver circuit. The first strategy relies on the calculation of the average value of the current flowing through all parallel-connected IGBTs. The second strategy is proposed by the authors on the basis of a current cross reference control scheme. Finally, the simulation and experimental results of the application of the two current sharing control algorithms are presented.

On the avalanche ruggedness of optimized termination structure for 600 V punch-through IGBTs

In this paper, the current paths in avalanche conditions of a Floating Field Ring (FFR) termination for a Punch-Through (PT) Insulated Gate Bipolar Transistor (IGBT) are analyzed. The design of the termination region is achieved with two different optimization techniques, and both static and dynamic electrical behavior are analyzed by means of 2D TCAD simulations, up to high current density levels. A comprehensive analysis of the Unclamped Inductive Switching (UIS) operation of the proposed terminations is carried-out with electro-thermal simulations. Although the behavior of both structures at low current levels is different, results show the same current crowding effect at the main junction for high current levels, resulting in a reduced conduction area of the overall termination, hence, of the avalanche reliability. Finally, experimental confirmation of filamentary current conduction during UIS test are detected on 600V commercial devices by means of transient infrared thermography.

Effect of Bandgap Narrowing on Performance of Modern Power Devices

The effect of the bandgap narrowing (BGN) on performance of power devices is investigated in detail in this paper. The analysis reveals that the change in the energy band structure caused by BGN can strongly affect the conductivity modulation of the bipolar devices resulting in a completely different performance. This is due to the modified injection efficiency under high-level injection conditions. Using a comprehensive analysis of the injection efficiency in a p-n junction, an analytical model for this phenomenon is developed. BGN model tuning has been proved to be essential in accurately predicting the performance of a lateral insulated-gate bipolar transistor (IGBT). Other devices such as p-i-n diodes or punch-through IGBTs are significantly affected by the BGN, while others, such as field-stop IGBTs or power MOSFETs, are only marginally affected.

Semi-quantitative analysis of the depth distribution of radiative recombination centers in silicon power devices by cross-sectional cathodoluminescence

A procedure to obtain the semi-quantitative depth distribution of radiative recombination centers in silicon power devices has been developed using cross-sectional cathodoluminescence (CL) by considering the nonradiative recombination on the surface of devices. Sharp luminescent peaks at 1.018 eV (W or I1), 1.040 eV (X or I3), and 0.790 eV (C) and a broad band about 0.90–1.05 eV in addition to near-band-edge emission were observed in the n-drift layer of the electron-irradiated lifetime-controlled punch-through insulated gate bipolar transistors using cross-sectional CL measurements. The semi-quantitative depth distributions of X, W, and C centers were obtained by the procedure. Each had a maximum value at the midpoint of the n-drift region, although electrons conventionally used to control carrier lifetime in power devices penetrated the entire device. One of the possible mechanisms for these distributions is the interaction of the X, W, and C centers with other point-like defects and impurities near the surface and the interface. The minority carrier (hole) diffusion length and the reduced recombination velocity in the devices are also extracted by this procedure.

1,200 V급 Trench Gate Field Stop IGBT 소자의 전기적 특성 향상 방안에 관한 연구

IGBT (insulated gate bipolar transistor) have received wide attention because of their high current conduction and good switching characteristics. To reduce the power loss of IGBT, the on state voltage drop should be lowered and the switching time should be shorted. However, there is Trade-off between the breakdown voltage and the on state voltage drop. To achieving good electrical characteristics, field stop IGBT (FS IGBT) is proposed. In this paper, 1,200 V planar gate non punch-through IGBT (planar gate NPT IGBT), planar gate FS IGBT and trench gate FS IGBT is designed and optimized. The simulation results are compared with each three structures. In results, we optain optimal design parameters and confirm excellence of trench gate FS IGBT. Experimental result by using medici, shows 40% improvement of on state voltage drop.

Total ionising dose effects on punch-through insulated gate bipolar transistors turn-on switching behaviour

This paper deals with the effects of 60Co gamma irradiation on punch-through commercial insulated gate bipolar transistor turn-on switching behaviour. The response of the threshold voltage and the turn-on switching parameters under three different in situ gate biases are described. Charge trapping in the gate oxide causes the decrease of the threshold voltage. It is shown that the decrease of this parameter and the decrease of the Miller plateau level result in a decrease of the collector current rise-time, the collector–emitter voltage fall-time, the turn-on switching energy and in an increase of the peak of the turn-on switching instantaneous power and of the turn-on overshoot collector current.

Cathodoluminescence Microcharacterization of Radiative Recombination Centers in Lifetime-Controlled Insulated Gate Bipolar Transistors

Cross-sectional cathodoluminescence (CL) measurements were applied to the study of electron-irradiated punch-through insulated gate bipolar transistors (IGBTs) to investigate the relationship between radiative recombination centers and electrical characteristics. IGBTs were additionally annealed at temperatures of 200–400 °C for 1 h. As annealing temperature rose, collector–emitter saturation voltage (VCES) decreased and current fall time (tf) increased. The cross-sectional CL measurements showed sharp luminescent peaks at 1018 meV (W or I1), 1040 meV (X or I3), and 790 meV (C) and a broad band at approximately 0.90–1.05 eV. As annealing temperature rose, the intensity of the W line decreased and that of the X line increased, suggesting that small self-interstitial clusters agglomerate and form stable, large self-interstitial clusters reducing the total number of self-interstitial clusters. The C line, which originated from an interstitial oxygen and carbon complex, showed no significant change. We consider that self-interstitial clusters play important roles in the electrical characteristics of lifetime-controlled IGBTs.

Analysis of the dynamic avalanche of punch through insulated gate bipolar transistor (PT-IGBT)

In the paper proposed here, we are studying the dynamic avalanche from experimental results first, dynamic avalanche is identified on a punch through insulated gate bipolar transistor (PT-IGBT) module 1200 V–300 A from Mitsubishi. Secondly, the phenomenon is analysed thanks to simple solid state devices equations. Numerical simulations are used to confirm experimental results. Simulation results allows us locating the active area of the dynamic avalanche during turn-off under over-current conditions. A PT-IGBT cell is described with MEDICI™, a finite element simulator. A mixed-mode simulation is performed thanks to MEDICI™ and SPICE™. The circuit simulated here is a buck topology with an inductive load. Finally, a thermal analysis is performed to estimate temperature increase due to dynamic avalanche.

턴-오프 시 PT-IGBT의 애노드 전압 강하 모델링

In this paper, transient characteristics of the Punch Through Insulated Gate Bipolar Transistor (PT-IGBT) have been studied. On the contrary to Non-Punch Through Insulated Gate Bipolar Transistor(NPT-IGBT), it has a buffer layer and reduces switching power loss. It has a simple drive circuit controlled by the gate voltage of the MOSFET and low on-state resistance of the bipolar junction transistor. The transient characteristics of the PT-IGBT have been analyzed analytically. Excess minority carrier and charge distribution in active base region, the rate of anode voltage with time are expressed analytically by adding the influence of buffer layer. The experimental data is obtained from manufacturer. The theoretical predictions of the analysis have been compared with the experimental data obtained from the measurement of a device(600 V, 15 A) and show good agreement.

A New 1200 V Punch Through-Insulated Gate Bipolar Transistor with Protection Circuit Employing Lateral Insulated Gate Bipolar Transistor and Floating p-Well Voltage Sensing Scheme

A new 1200 V punch through-insulated gate bipolar transistor (PT-IGBT) with a protection circuit employing a lateral IGBT (LIGBT) and a floating p-well voltage sensing scheme is proposed and implemented by fabricating the main IGBT and gate voltage pull-down circuit using the widely used planar IGBT process. The detection of the fault and gate voltage pull-down operations is achieved using the floating p-well sensing scheme. The LIGBT used as a pull-down transistor reduces the area of the protection circuit due to the enhanced current handling capability. The voltage saturation effect of a floating p-well voltage under the high voltage condition provides the 1200 V PT-IGBT with a reliable and rapid protection by preventing the gate oxide failure of the pull-down LIGBT and eliminating the blanking filter.

A New 600 V Punch Through-Insulated Gate Bipolar Transistor with the Monolithic Fault Protection Circuit Using the Floating p-Well Voltage Detection

A new fault sensing scheme of the insulated gate bipolar transistor (IGBT) employing the floating p-well, which detects the over-voltage of the floating p-well under the short circuit fault condition, is proposed and implemented by fabricating the main IGBT and gate voltage pull-down circuit using the widely used planar IGBT process. The floating p-well structure also improves the avalanche energy of IGBT in addition to detecting the fault signal. The detection of fault and gate voltage pull-down operation is achieved by the proposed fault protection scheme employing the floating p-well voltage detection. The proposed fault protection circuit was measured under the hard switching fault (HSF) and fault under load (FUL) conditions. The normal switching behavior of the main IGBT with the proposed protection circuit was also investigated under inductive load switching conditions.

Investigation of Short-Circuit Failure Limited by Dynamic-Avalanche Capability in 600-V Punchthrough IGBTs

Short-circuit-failure energy of insulated gate bipolar transistors (IGBTs) is generally known to be constant, depending on the thermal capacity of the devices. However, apart from the intrinsic thermal-failure limit, a premature short-circuit failure was observed for 600-V punchthrough (PT) IGBTs at turn-off transition. The observed failure seems irrelevant to the electrical-failure mode as well as the thermal-failure mode, rather, it depends on the dynamic-breakdown voltage of the device. In this paper, with comprehensive investigations into an instant short-circuit failure, it is shown that the observed short-circuit failure of the PT IGBTs results from insufficient avalanche capability, which is initiated by dynamic-avalanche breakdown and can severely degrade the short-circuit ruggedness of the PT IGBTs independent of the duration of the short-circuit event.

Two-step parameter extraction procedure with formal optimization for physics-based circuit simulator IGBT and p-i-n diode models

A practical and accurate parameter extraction method is presented for the Fourier-based-solution physics-based insulated gate bipolar transistor (IGBT) and power diode models. The goal is to obtain a model accurate enough to allow switching loss prediction under a variety of operating conditions. In the first step of the extraction procedure, only one simple clamped inductive load test is needed for the extraction of the six parameters required for the diode model and of the 12 and 15 parameters required for the nonpunch-through (NPT) and punch-through (PT) IGBT models, respectively. The second part of the extraction procedure is an automated formal optimization step that refines the parameter estimation. Validation with experimental results from various structures of IGBT demonstrates the accuracy of the proposed IGBT and diode models and the robustness of the parameter extraction method.

Temperature Effects on Trench-Gate Punch-Through IGBTs

The switching characteristics (turn-on and turn-off) and forward conduction drop of trench-gate punch-through insulated gate bipolar transistors (IGBTs) are examined over a temperature range of from -50/spl deg/C to 125/spl deg/C. An analytical description of the forward conduction voltage drop is presented based on temperature dependencies of the appropriate physical parameters and mechanisms. A physics-based PSpice model, incorporating much of the device behavior, is also described. Results from the model are compared to experimental waveforms.