Punch-through Insulated Gate Bipolar Transistors Research Articles

New anode design concept of 600 V thin wafer PT-IGBT with very low dose P-buffer and transparent P-emitter

A 600 V thin wafer PT-IGBT (punch through insulated gate bipolar transistor) is proposed, having a new concept anode design. The proposed PT-IGBT has a very low dose p-type layer, named the ‘p-buffer’, between a transparent p-emitter and an n-buffer layer. This provides a practical design for easy fabrication without deteriorating the good feature of thin wafer PT-IGBTs. The n-buffer dose and p-emitter dose can be precisely controlled by the dose levels of the two ion implantations. This enables precise control of the p-emitter injection efficiency. An oscillation in the turn-off waveforms also disappears for the proposed PT-IGBT with p-buffer layer, because smooth turn-off is achieved by the small tail current. The total power loss is not affected by the small tail loss.

A Systematic Hard- and Soft-Switching Performances Evaluation of 1200V Punchthrough IGBT Structures

The performances of various 1200 V insulated gate bipolar transistor (IGBT) structures for hard- and soft-switching (both the zero-voltage and the zero-current switching) at high temperature and under various test conditions are investigated in detail. A comparison is made between a conventional planar punchthrough IGBT (P-IGBT) using global lifetime control, a trench punchthrough IGBT (T-IGBT) using local lifetime control and a enhanced planar punchthrough IGBT (N-IGBT) also using the local lifetime control process. A simple and effective specific test circuit allows hard- and soft-switching operating modes, and provides also an independent control on the test parameters (load current, clamping voltage, gate resistance, temperature, dead times). It is highlighted that the local lifetime control is very efficient at high temperature reducing especially the turn-off losses. Furthermore, the T-IGBT exhibits very good performances during hard- and soft-switching turn-off, but this is not the case during hard-switching and zero-voltage switching turn-on. Due to its high input capacitance, the hard-switching turn-on losses are relatively high. Regarding the N-IGBT, it presents good performances under hard-switching and also zero-voltage switching. However, like the T-IGBT, its structure has a strong inductance behavior during zero-voltage turn-on increasing the conductivity modulation lag and also the voltage spike leading to high losses. All these data allow to provide useful information for the devices modeling, design, and optimization.

A new punch-through IGBT having a new n-buffer layer

Insulated gate bipolar transistors (IGBTs) based on the non-punch-through (NPT) design approach exhibit excellent safe operating area (SOA) and short-circuit endurance, a positive temperature coefficient of on-state voltage over the operating current range, and low silicon cost. These merits have supported the development and commercialization of NPT IGBTs above the 1200-V class. However, the need for quite thin silicon to obtain competitive on-state losses at 1200-V and below classes has hindered the use of the NPT approach in this area. A new punch-through (PT) IGBT has been developed which exhibits the merits of the NPT approach, rugged SOA and short-circuit endurance, while also having a better tradeoff relation between on-state voltage and turn-off loss than either existing NPT or third-generation PT IGBTs.

Non-destructive extraction of technological parameters for numerical simulation of conventional planar punch-through IGBT

Two dimensional (2D) physics-based simulation of power semiconductor devices provides valuable information about the dynamic mechanisms within the devices, thus improving the understanding of device performance in various applications. Numerical simulation requires several technological parameters such as doping, dimensions of various regions and carrier lifetime. Destructive methods are available, but they are quite expensive and require sophisticated equipment. This article describes an original non-destructive technological parameter extraction methodology for conventional planar punch-through (PT) insulated gate bipolar transistor (IGBT) based on simple electrical measurements to obtain an equivalent physics-based model of the real device. To verify the accuracy of these extracted parameters, a 2D PT-IGBT structure is implemented in a physics-based finite element simulator. A good match between simulated and experimental results validates this methodology.

Thermal stability of IGBT high-frequency operation

Thermal stability of high-frequency insulated gate bipolar transistor (IGBT) operation is studied in this paper. The nonpunch-through IGBT is found to be stable when operated within its rated temperature. Thermal runaway occurs with punch-through IGBTs at temperatures below the maximum junction temperature when operated at high frequency at well below rated current, with snubber or soft-switching circuits.

A comparison of IGBT models for use in circuit design

In choosing an accurate insulated gate bipolar transistor (IGBT) model for power electronic circuit design, physics-based models are frequently preferred due to their high accuracy and fast simulation speed in comparison to other types of models. In this paper, an experimental comparison of two such models is made, using parameters extracted from experimental measurements. The comparison focuses on two particular IGBTs-the BUP202 and the BUK854-representing the two common types of IGBT, respectively, the nonpunchthrough and the punchthrough IGBT. The models are investigated for the IGBT's operation in three situations typical of low-power (600 V, 10 A) applications.

Failure mechanisms of IGBTs under short-circuit and clamped inductive switching stress

The application of insulated gate bipolar transistors (IGBTs) in high-power converters subjects them to high-transient electrical stress such as short-circuit switching and turn-off under clamped inductive load (CIL). Robustness of IGBTs under high-stress conditions is an important requirement. Due to package limitations and thermal parameters of the semiconductor, significant self-heating occurs under conditions of high-power dissipation, eventually leading to thermal breakdown of the device. The presence of a parasitic thyristor also affects the robustness of the device. In order to develop optimized IGBTs that can withstand high-circuit stress, it is important to first understand the mechanism of device failure under various stress conditions. In this paper, failure mechanisms during short-circuit and clamped inductive switching stress are investigated for latchup-free as well as latchup-prone punchthrough IGBTs. It is shown that short-circuit and clamped inductive switching cannot be considered equivalent in the evaluation of a device safe operating area (SOA). The location of thermal failure of latchup-free punchthrough IGBTs is shown to be different for the two switching stresses.

Maximum operating junction temperature of PT andNPT IGBTs

The maximum operating junction temperatures of punch-through (PT) and non-punch-through (NPT) insulated gate bipolar transistors (IGBTs) at high frequency are investigated experimentally. The maximum junction temperature of the PT IGBT varies with circuit conditions and is in the range 115–170°C. The NPT IGBT can typically operate at junction temperatures up to 230°C in various circuits.

IGBT dynamics for clamped inductive switching

Clamped inductive switching performance of insulated gate bipolar transistors (IGBTs) have been studied in detail with the aid of extensive measurements and numerical simulations. Internal dynamics of a latch-up free punch-through IGBT during clamped inductive switching is studied using two-dimensional (2-D) mixed device and circuit simulations incorporating the self-heating mechanism. Failure of IGBT during inductive load turn-off is shown to occur due to thermally assisted carrier multiplication at the reverse biased p-base n-drift region junction under the emitter contact.

A study of the internal device dynamics of punch-through and nonpunch-through IGBTs under zero-current switching

The effective use of power insulated gate bipolar transistors (IGBTs) requires a good understanding of their internal device physics. This understanding is essential for the optimal interaction among the IGBTs, their snubber elements and the power circuit in which the IGBTs operate. As switching frequencies are pushed to higher values, switching loss reduction becomes an essential part of the design and optimization process. Soft switching techniques such as zero-voltage switching (ZVS) and zero-current switching (ZCS) are widely used for this purpose. This study provides an insight into the internal dynamic behavior of IGBTs under zero-current switching. The latter is accomplished through mixed-mode simulation, providing the necessary insight for the improvement of circuit and device performance. In particular, the authors have analyzed the behavior of the negative current in nonpunch-through (NPT) devices after the first zero-current crossing and the effect of the turn-off delay on the tail current. They have also experimentally characterized punch-through (PT) and NPT IGBTs to confirm the insights provided by the mixed-mode simulation.