Pump Clock Research Articles

A Small Ripple and High-Efficiency Wordline Voltage Generator for 3-D nand Flash Memories

This article presents a small ripple and high-efficiency wordline (WL) voltage generator to supply voltage to the selected/unselected WLs for program and read operation in 3-D NAND Flash memories. With the proposed scheme of dynamic pump clock voltage and frequency scaling, the output ripple voltage can be minimized to reduce the variation of threshold voltage of the memory cells and the efficiency can be improved to save power consumption at the same time. What is more, with the minimized ripple, the requirement for power supply rejection ratio (PSRR) of the high-voltage regulator used to provide low noise WL voltage can be reduced. The proposed WL voltage generator has been fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> triple-well CMOS process and the core chip size is 0.53 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . While operating at a 1.8-V supply, the measurement results show that the ripple voltage is 5.5 mV at 12-V output voltage under the typical 50-pF cap load conditions of 3-D NAND Flash memories. Furthermore, the output ripple hardly varies with the increase of load current. In addition, the maximum power efficiency is 49% at 400 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> and can be maintained over 30% in the 50–450- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> current load range.

A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

Sub-threshold start-up circuit with dynamic body-biasing for boost converters in thermoelectric energy harvesting

A 260 mV start-up charge pump and oscillator applying dynamic bulk-biasing (DBB) for step-up converters in thermal energy harvesting is presented and validated through SPICE simulation. This DBB employs a dynamic substrate control circuit (DSCC) directly controlled by the pump clock. It can dynamically reduce sub-threshold leakages during off-state and increase conduction during on-state. This is necessary for thermoelectric harvesters with output voltages of $$\le $$ 300 mV. Performance of this DBB start-up circuit is compared to those of conventional reverse and forward bulk-biasing charge pumps. According to simulated results using the TSMC180 nm CMOS model, DBB reduces kick-start voltage to 225 mV. This proposed circuit has a 1.44 $$\times $$ –52 $$\times $$ better overall figure-of-merit (FOM) compared with conventional circuits at a supply voltage of 260 mV. It can generate 50 μW of maximum power with an unregulated output of 2.5 V within 171 μs from cold start-up. This overall improvement in speed, power and pumping efficiency facilitates battery-less solutions in biomedical applications for wearable/implanted micro-devices.

A Regulated Temperature-Insensitive High-Voltage Charge Pump in Standard CMOS Process for Micromachined Gyroscopes.

Micromachined gyroscopes require high voltage (HV) for actuation and detection to improve its precision, but the deviation of the HV caused by temperature fluctuations will degrade the sensor’s performance. In this paper, a high-voltage temperature-insensitive charge pump is proposed. Without adopting BCD (bipolar-CMOS-DMOS) technology, the output voltage can be boosted over the breakdown voltage of n-well/substrate diode using triple-well NMOS (n-type metal-oxide-semiconductor) transistors. By controlling the pumping clock’s amplitude continuously, closed-loop regulation is realized to reduce the output voltage’s sensitivity to temperature changes. Besides, the output level is programmable linearly in a large range by changing the reference voltage. The whole circuit has been fabricated in a 0.18-m standard CMOS (complementary metal-oxide-semiconductor) process with a total area of 2.53 mm. Measurements indicate that its output voltage has a linear adjustable range from around 13 V to 16.95 V, and temperature tests show that the maximum variations of the output voltage at are less than 1.1%.

Optimization of Sine-Wave Clocking for High-Frequency AC-DC Conversion.

Wireless energy harvesting devices convert received AC energy into DC voltages suitable to power the back-end functionality of the devices. The low energy available to the devices require high AC-DC conversion efficiency in order for enough power to be delivered to the load. This paper presents a model to characterize loss through charge pump cells in wireless energy harvesting devices. The proposed model includes the time-domain effects of the input radio-frequency (RF) energy wave and provides additional insight into how clock and switch parameters along with architecture considerations can be used to improve the efficiency of AC-DC conversion. Results are verified using simulation in a 0.18-μm CMOS technology. We show the impact of threshold voltage on reverse conduction and the limitations on increasing transistor switch sizes to support high current loads. Design examples use the presented model to optimize design parameters to decrease loss in the charge pump. We compare the performance between sine-wave and square-wave clocked charge pumps to show the trade-off between charge pump loss and clock generation power consumption. Furthermore, the benefits of easily computing architectural changes is demonstrated using the proposed model showing how the calculated equivalent resistance can be used to determine the benefits of mixed-mode clocking.

Abstract #231: Insulin Pump Clock Glitches: A Word of Caution to Clinicians

Abstract #231: Insulin Pump Clock Glitches: A Word of Caution to Clinicians

A 300-mV ΔΣ Modulator Using a Gain-Enhanced, Inverter-Based Amplifier for Medical Implant Devices

An ultra-low-voltage low-power switched-capacitor (SC) delta-sigma (ΔΣ) modulator running at a supply voltage as low as 300 mV is presented for biomedical implant devices, e.g., cardiac pacemakers. To reduce the supply voltage, an inverter-based amplifier is used in the integrators, whose DC gain and gain-bandwidth (GBW) are boosted by a simple current-mirror output stage. The full input-feedforward loop topology offers low integrators internal swing, supporting ultra-low-voltage operation. To demonstrate the concept, a second-order loop topology was chosen. The entire modulator operates reliably against process, voltage and temperature (PVT) variations from a 300 mV ± 10% supply voltage only, while the switches are driven by a charge pump clock boosting scheme. Designed in a 65 nm CMOS technology and clocked at 256 kHz, the simulation results show that the modulator can achieve a 64.4 dB signal-to-noise ratio (SNR) and a 60.7 dB signal-to-noise and distortion ratio (SNDR) over a 1.0 kHz signal bandwidth while consuming 0.85 μW of power.

A bipolar output voltage pulse transformer boost converter with charge pump assisted shunt regulator for thermoelectric energy harvesting

This system presents an energy harvesting system that generates bipolar output voltage (±1 V) based on a miniature 1:1 turn-ratio pulse transformer boost converter using sub-threshold level input voltage source. A shunt regulator is designed using six-transistor Schmitt-Trigger core to limit the boost converter output voltage. Another power stage, i.e. a fully integrated on-chip single-stage cross-coupled charge pump, then generates 3 V output from the unused extra output power of boost converter, which is shunted otherwise. The increased voltage headroom generated is instrumental for sensor, analog and RF circuits. Charge pump clock frequency is designed to adaptively tracking the input voltage, which is sensed using power-saving time-domain digital technique. Based on a standard CMOS 0.13-µm technology, chip measurement verified the operations of the boost converter, shunt regulator and bipolar charge pump prototypes, respectively. Simulations confirmed the full system operations. During start-up, the system only requires minimum start-up input voltage of 36 mV at input power of 5.8 µW.

A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170C

First-ever 28 nm embedded split-gate MONOS (SG-MONOS) flash macros have been developed to increase memory capacity embedded in micro controller units and to improve performance over wide junction temperature range from $-40^{\circ}{\hbox {C}}$ to 170 $^{\circ}{\hbox {C}}$ as demanded strongly in automotive uses. Much attention has been paid to the degradation of the reliability characteristics along with the process shrinkage. Temperature-adjusted word-line overdrive scheme improves random read access frequency by 15% and realizes both of 6.4 GB/s read throughput by 200 MHz no-wait random access of code flash macros and more than ten times longer TDDB lifetime of WL drivers. Temperature-adaptive step pulse erase control (TASPEC) improves the TDDB lifetime of dielectric films between metal interconnect layers by three times. TASPEC is particularly useful for a data flash macro with one million rewrite cycles. Source-side injection (SSI) program with negative back-bias voltage achieves 63% reduction of program pulse time and, consequently, realizes 2.0 MB/s write throughput of code flash macros. A spread spectrum clock generation and a clock phase shift technique are introduced for charge pump clock generation in order to suppress EMI noise due to high write throughput of code flash macros, and peak power of EMI noise is reduced by 19 dB.

Total Jitter of Delay-Locked Loops Due to Four Main Jitter Sources

There are four main sources of jitter in delay-locked loops (DLLs). In this paper, DLL's jitter due to uncertainties in these sources of jitter is calculated. Time domain equations of DLL are introduced, which are the key parameters to obtain a closed-form equation related to jitter of DLL in the presence of noisy phase-frequency detector, charge pump, delay cells, and reference clock. First, DLL's jitter at the output of each delay cells due to each sources of the jitter will be calculated. Then, the obtained equations are used to calculate the total jitter at the output of all stages. Finally, a DLL is designed in the 0.18-μm CMOS technology to validate the obtained equations.

Pitfalls of insulin pump clocks: technical glitches that may potentially affect medical care in patients with diabetes.

The objective was to raise awareness about the importance of ensuring that insulin pumps internal clocks are set up correctly at all times. This is a very important safety issue because all commercially available insulin pumps are not GPS-enabled (though this is controversial), nor equipped with automatically adjusting internal clocks. Special attention is paid to how basal and bolus dose errors can be introduced by daylight savings time changes, travel across time zones, and am-pm clock errors. Correct setting of insulin pump internal clock is crucial for appropriate insulin delivery. A comprehensive literature review is provided, as are illustrative cases. Incorrect setting can potentially result in incorrect insulin delivery, with potential harmful consequences, if too much or too little insulin is delivered. Daylight saving time changes may not significantly affect basal insulin delivery, given the triviality of the time difference. However, bolus insulin doses can be dramatically affected. Such problems may occur when pump wearers have large variations in their insulin to carb ratio, especially if they forget to change their pump clock in the spring. More worrisome than daylight saving time change is the am-pm clock setting. If this setting is set up incorrectly, both basal rates and bolus doses will be affected. Appropriate insulin delivery through insulin pumps requires correct correlation between dose settings and internal clock time settings. Because insulin pumps are not GPS-enabled or automatically time-adjusting, extra caution should be practiced by patients to ensure correct time settings at all times. Clinicians and diabetes educators should verify the date/time of insulin pumps during patients' visits, and should remind their patients to always verify these settings.

An Energy Efficient $V_{\rm PP}$ Generator With Fast Ramp-Up Time for Mobile DRAM

An energy efficient <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> generator with fast ramp-up time for mobile DRAM is presented in this paper. Instead of using a fixed pumping clock frequency as in the conventional <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> generator, the proposed <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> generator adopts a voltage-controlled oscillator (VCO) and uses variable pumping frequencies to improve the ramp-up time as well as energy efficiency. Numerical results show that the VCO based <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> generators achieve energy savings of up to 34% with 40% improvement on ramp-up time when compared to the conventional ring oscillator (RO) based design. Our proposed <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> generator, which uses a three-stage voltage doubler as a charge pump, was implemented and fabricated in CMOS 0.13 μm process. The <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> generator chip's core occupies 0.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area and consumes 1162 nJ (average power of 47.8 mW during 24 μs ramp-up time) while generating 3.0 V output voltage with 1.0 nF load capacitor, 2.0 mA current load and 1.2 V supply voltage.

2- Input AND Gate For Fast Gating and Switching Based On XGM Properties of InGaAsP Semiconductor Optical Amplifier

We report on an all-optical AND-gate using simultaneous Four-Wave Mixing (FWM) and Cross-Gain Modulation (XGM) in a semiconductor optical amplifier (SOA). The operation of the proposed AND gate is simulated and the results demonstrate its effectiveness. This AND gate could provide a new possibility for all-optical computing and all-optical routing in future all-optical networks. In an AND ( AB ) gate, Boolean is firstly obtained by using signal B as a pump beam and clock signal as a probe beam in SOA-1. By passing signal A as a probe beam and as a pump beam through SOA-2, Boolean AB is acquired. Proposed optical logic unit is based on coupled nonlinear equations describing XGM and FWM effects. These equations are first solved to generate the pump, probe and conjugate pulses in a SOA. The pulse behavior are analyzed and applied to realize behavior of all-optical AND gate and its function is verified with the help of waveform and analytical assumption.

Charge Pump Design for TFT-LCD Driver IC Using Stack-MIM Capacitor

A cross-coupled charge pump with internal pumping capacitor, which is advantageous from a point of minimizing TFT-LCD driver IC module, is newly proposed in this paper. By using NMOS and PMOS diodes connected to boosting nodes from VIN nodes, the pumping node is precharged to the same value at the pumping node in starting pumping. Since the first-stage charge pump is designed differently from the other stage pumps, a back current of pumped charge from charge pumping node to input stage is prevented. As a pumping clock driver is located in front of pumping capacitor, the driving capacity is improved by reducing a voltage drop of the pumping clock line from parasitic resistor. Finally, a layout area is decreased more compared with the conventional cross-coupled charge pump by using a stack-MIM capacitor. A proposed charge pump for TFT-LCD driver IC is designed with 0.13μm triple-well DDI process, fabricated, and tested.

Proposal for PPLN-Based All-Optical NRZ-to-CSRZ, RZ-to-CSRZ, NRZ-DPSK-to-CSRZ-DPSK, and RZ-DPSK-to-CSRZ-DPSK Format Conversions

A simple realization of 40-Gb/s all-optical format conversions from nonreturn-to-zero (NRZ) to carrier-suppressed return-to-zero (CSRZ), from return-to-zero (RZ) to CSRZ, from NRZ differential phase-shift keying (NRZ-DPSK) to CSRZ-DPSK, from RZ-DPSK to CSRZ-DPSK are proposed and numerically demonstrated based on cascaded second-order nonlinearities in a periodically poled lithium niobate waveguide. A carrier-suppressed pump clock is adopted. The spectra, waveforms, eye diagrams, and constellation diagrams are investigated. Multicasting, multichannel, and ultrahigh-speed (160 Gb/s) operations are also numerically demonstrated.

A Charge Pump Design with Internal Pumping Capacitor for TFT-LCD Driver IC

A cross-coupled charge pump with internal pumping capacitor, witch is advantages from a point of minimizing TFT-LCD driver IC module, is newly proposed in this paper. By using a NMOS and a PMOS diode connected to boosting node from VIN node, the pumping node is precharged to the same value each pumping node at start pumping operation. Since the lust-stage charge pump is designed differently from the other stage pumps, a back current of pumped charge from charge pumping node to input stage is prevented. As a pumping clock driver is located the font side of pumping capacitor, the driving capacity is improved by reducing a voltage drop of the pumping clock line from parasitic resistor. Finally, a layout area is decreased more compared with conventional cross-coupled charge pump by using a stack-MIM capacitors. A proposed charge pump for TFT-LCD driver IC is designed with triple-well DDI process, fabricated, and tested.

Time Synching or Time Sinking?

Diabetes Technology & TherapeuticsVol. 7, No. 5 EditorialTime Synching or Time Sinking?Daniel J. Crowe and David C. KlonoffDaniel J. CroweSearch for more papers by this author and David C. KlonoffSearch for more papers by this authorPublished Online:21 Oct 2005https://doi.org/10.1089/dia.2005.7.663AboutSectionsPDF/EPUB ToolsPermissionsDownload CitationsTrack CitationsAdd to favorites Back To Publication ShareShare onFacebookTwitterLinked InRedditEmail "Time Synching or Time Sinking?." , 7(5), pp. 663–664FiguresReferencesRelatedDetailsCited byIncorrect AM/PM Insulin Pump Clock Settings Can Result in an Unstable Insulin Dosing Feedback Loop15 November 2016 | Journal of Diabetes Science and Technology, Vol. 11, No. 4American Association Of Clinical Endocrinologists And American College Of Endocrinology 2016 Outpatient Glucose Monitoring Consensus StatementEndocrine Practice, Vol. 22, No. 2Pitfalls of Insulin Pump Clocks2 July 2014 | Journal of Diabetes Science and Technology, Vol. 8, No. 6Insulin Pump Safety Meeting: Summary Report1 March 2009 | Journal of Diabetes Science and Technology, Vol. 3, No. 2Predicted Blood Glucose from Insulin Administration Based on Values from Miscoded Glucose Meters1 July 2008 | Journal of Diabetes Science and Technology, Vol. 2, No. 4Function and Accuracy of Glucose Sensors Beyond Their Stated Expiry Date Rudolf Chlup, Daniela Jelenová, Karolina Chlupová, Jana Zapletalová, Ludmila Chlupová, and Josef Bartek29 August 2006 | Diabetes Technology & Therapeutics, Vol. 8, No. 4 Volume 7Issue 5Oct 2005 InformationCopyright 2005, Mary Ann Liebert, Inc.To cite this article:Daniel J. Crowe and David C. Klonoff.Time Synching or Time Sinking?.Diabetes Technology & Therapeutics.Oct 2005.663-664.http://doi.org/10.1089/dia.2005.7.663Published in Volume: 7 Issue 5: October 21, 2005PDF download

A low-ripple poly-Si TFT charge pump for driver-integrated LCD panel

A low-ripple charge pump for voltage up-conversion is described which was implemented in a poly-Si thin-film-transistor (TFT) technology for driver-integrated liquid-crystal-display (LCD) panels. The ripple voltage of the charge pump is reduced by employing a multi-phase clocking method. The charge pump was implemented in a poly-Si TFT technology. For output current of 100/spl mu/A, filtering capacitor of 100 pF and pumping clock frequency of 1 MHz, the measured ripple voltage of the proposed charge pump is 135 mV while that of conventional Dickson charge pump is 590 mV. The measured pumping efficiencies of the Dickson and proposed 4-phase clocking charge pump are 59% and 65%, respectively.

P-13: A Novel Simple 2-phase Clock of Charge Pump for LTPS Integrated Circuits

High driving current (>2mA) and high efficiency (∼80%) charge pump DC/DC converter using simple 2-phase pump clock was developed. The circuit shows less dependence on process caused device variation, which is very suitable for present mature LTPS process, especially for large mother glass. The good characteristics make it highly applicable to LCD and OEL panels