Pulsed Stress Conditions Research Articles

Modeling of the degradation of CMOS inverters under pulsed stress conditions from ‘on-the-fly’ measurements

In this work, an ‘on-the-fly’ measurement technique for the monitoring of CMOS inverters performance degradation is presented. This technique allows the characterization of the circuit degradation simultaneously with the applications of the stress. In our experiments, the inversion voltage (VINV) shifts measured during the application of pulsed voltage stresses at the input. It is demonstrated that the shifts can be described by a power law that accounts for the stress time and voltage dependences. Moreover, the circuit degradation has been correlated to the NMOS and PMOS degradations. The results show that the degradation of the CMOS inverter can be evaluated from an analytical equation that considers only the shifts of two parameters (threshold voltage VTH, and mobility µ) of the two transistors in the inverter.

Ultra sensitive measurement of dielectric current under pulsed stress conditions

In order to perform electrical analysis of dielectrics in integrated circuits, various techniques have been employed in the past. Many of these included the use of large test structures and long measurement times to characterize the dielectric. This work presents a new method that circumvents both of these limitations. Analyzing the leakage behavior of the dielectric by charge measurements allows to use small structures and perform measurements with very short characterization times. This reduces the destructive nature of dielectric I–V-characterization significantly. It allows analysis of intrinsic dielectric behavior from small structures. A dielectric is analyzed to show the applicability of this procedure. The new analysis method enables measurements beyond previously available parameter ranges.

NBTI related degradation and lifetime estimation in p-channel power VDMOSFETs under the static and pulsed NBT stress conditions

The effects of static and pulsed NBT stressing on threshold voltage in p-channel power VDMOSFETs are analysed, and the results are compared in terms of the effects on device lifetime. The results obtained by both “1/VG” and “1/T” models, which are used for extrapolation to normal operation voltages and temperatures, respectively, indicate the device lifetime could be much longer under the pulsed stress conditions than under the static ones. It is also shown that lifetime tends to increase with decreasing the duty cycle of pulsed stress voltage applied.

Threshold voltage instabilities in p-channel power VDMOSFETs under pulsed NBT stress

Threshold voltage instabilities induced in p-channel power VDMOSFETs by pulsed negative bias temperature stressing are presented and compared with corresponding instabilities found after the static NBT stress. Degradation observed under the pulsed stress conditions depends on the frequency and duty cycle of stress voltage pulses, and is generally lower than the one found after the static NBT stress. Optimal frequency and duty cycle ranges for application of investigated devices are proposed as well. By selecting an appropriate combination of frequency range (1 kHz < f < 5 kHz) and duty cycle (about 25%), the pulsed stress-induced Δ V T can be reduced to a quarter of Δ V T found after the static NBT stress.

Degradation of static and dynamic behavior of CMOS inverters during constant and pulsed voltage stress

We study the degradation of CMOS inverters under DC and pulsed stress conditions before the occurrence of the gate oxide breakdown. Our results show an overall speed reduction, caused by the transistor drain current drop, and a leftward shift of the inverter voltage transfer characteristics, due to a larger degradation of the PMOSFET as compared to the NMOSFET. We attribute this behavior to the build-up of defects/trapped charge featuring a different kinetics in P- and N-type MOSFETs.

Low electric field breakdown of thin SiO/sub 2/ films under static and dynamic stress

A comprehensive study of Time-Dependent Dielectric Breakdown (TDDB) of 6.5-, 9-, 15-, and 22-nm SiO/sub 2/ films under dc and pulsed bias has been conducted over a wide range of electric fields and temperatures. Very high temperatures were used at the wafer level to accelerate breakdown so tests could be conducted at electric fields as low as 4.5 MV/cm. New observations are reported for TDDB that suggest a consistent electric field and temperature dependence for intrinsic breakdown and a changing breakdown mechanism as a function of electric field. The results show that the logarithm of the median-test-time-to failure, log (t/sub 50/), is described by a linear electric field dependence with a field acceleration parameter that is not dependent on temperature. It has a value of approximately 1 decade/MV/cm for the range of oxide thicknesses studied and shows a slight decreasing trend with decreasing oxide thickness. The thermal activation E/sub a/ ranged between 0.7 and 0.95 eV for electric fields below 9.0 MV/cm for all oxide thicknesses. TDDB tests conducted under pulsed bias indicate that increased dielectric lifetime is observed under unipolar and bipolar pulsed stress conditions, but diminishes as the stress electric field and oxide thickness are reduced. This observation provides new evidence that low electric field aging and breakdown is not dominated by charge generation and trapping.